Formal Verification Engineer — RTL, Proofs & Verification

NVIDIA Gruppe; Santa Clara (CA); On-site; USD 100,000 - 166,750; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA Gruppe is seeking a Formal Verification Engineer in Santa Clara, CA. The role involves formal verification of RTL units for chip designs, requiring strong analytical skills and knowledge of architectural details.

Ideal candidates should hold a BS or MS in CS/CE/EE/Mathematics and have experience in formal methods and HDL tools like Verilog and SystemVerilog. A strong communication ability to collaborate effectively is also essential.

The salary ranges from $100,000 to $166,750 for Level 1 and includes equity and benefits.

Qualifications

• Strong analytical skills to solve difficult problems.
• Knowledge/Experience in formal verification techniques.
• Hands‑on experience with HDLs such as Verilog / SystemVerilog.
• Ability to understand RTL quickly.

Responsibilities

• Develop comprehensive FV testplan documents.
• Identify key behaviors for verification of DUT.
• Develop verification environments including environment assumptions.
• Debug RTL to identify failure scenarios.
• Create automation scripts for the verification process.

Skills

Analytical skills

Formal verification techniques

Knowledge of CPU/GPU designs

Communication skills

Education

BS or MS in CS/CE/EE/Mathematics

Tools

Verilog

SystemVerilog

Formal Verification Tools

Job description

NVIDIA Gruppe is seeking a Formal Verification Engineer in Santa Clara, CA. The role involves formal verification of RTL units for chip designs, requiring strong analytical skills and knowledge of architectural details.

Ideal candidates should hold a BS or MS in CS/CE/EE/Mathematics and have experience in formal methods and HDL tools like Verilog and SystemVerilog. A strong communication ability to collaborate effectively is also essential.

The salary ranges from $100,000 to $166,750 for Level 1 and includes equity and benefits.