Embedded AI Engineer: Edge Hardware & Kernels

Aimlroles; Northern (KY); Hybrid; USD 120,000 - 190,000; Full time

Job summary

Deepgram is seeking an Embedded AI Engineer to work on the Partner Platform Engineering team, writing and optimizing kernels for edge hardware and collapsing models onto device-specific units. You will tailor quantization, fusion, and compilation to meet strict latency and power budgets, collaborating with Applied ML Engineers to land models on new silicon.

This senior/staff-level role emphasizes hands-on kernel work, hardware familiarity, and close work with vendor toolchains to enable

Qualifications

• Experience delivering production systems on resource-constrained hardware.
• Strong proficiency in C/C++ and/or Rust.
• Hands-on experience with model optimization for on-device deployment.
• Familiarity with edge inference runtimes (ONNX/TensorRT/TFLite).
• Understanding of hardware–software interaction (CPU/GPU/NPU, memory hierarchies).
• Experience with bare-metal or RTOS environments (FreeRTOS/Zephyr).
• Strong communication skills and a builder mindset.

Responsibilities

• Write and optimize custom kernels and operators for non-NVIDIA accelerators and embedded SoCs.
• Own target-side optimization including quantization and layout for latency and power targets.
• Integrate with vendor NPU/DSP toolchains and extend runtimes with custom operators.
• Deliver reusable kernels and runtime components for Applied ML Engineers to adapt models.
• Build performance-critical runtime code for embedded environments (embedded Linux, RTOS).
• Set per-platform benchmarks and validate latency, power, memory, and utilization.
• Collaborate with silicon vendors for SDK integration and low-level tuning.

Skills

C/C++

Rust

Embedded systems

Edge AI

Performance tuning

Education

BSc in CS/EE

Tools

ONNX Runtime

TensorRT

TFLite

ExecuTorch

Job description

Deepgram is seeking an Embedded AI Engineer to work on the Partner Platform Engineering team, writing and optimizing kernels for edge hardware and collapsing models onto device-specific units. You will tailor quantization, fusion, and compilation to meet strict latency and power budgets, collaborating with Applied ML Engineers to land models on new silicon.

This senior/staff-level role emphasizes hands-on kernel work, hardware familiarity, and close work with vendor toolchains to enable