DSP Software Engineer - Heterogeneous SoCs

Teradar; Boston (MA); On-site; USD 140,000 - 210,000; Full time

Job summary

Teradar, founded in Boston, develops a terahertz vision sensor for automotive applications. We are seeking a skilled engineer to architect multicore radar software on an SoC, balancing workloads and optimizing memory and inter-core communication.

You will implement kernels, validate with virtual platforms, and tune performance across the pipeline. The role demands C/C++, SIMD/VLIW proficiency, RTOS/bare-metal experience, and a deep understanding of radar concepts such as FMCW, FFTs, CFAR, and

Qualifications

• Experience building multicore embedded software for an SoC.
• Ability to partition workloads and balance load across cores.
• Hands-on DMA-driven data movement and memory hierarchy management.
• Familiarity with real-time OS concepts and boot flow.
• Proficiency in C/C++ with SIMD/VLIW intrinsics.

Responsibilities

• Architect and implement multicore software for radar signal processing on an SoC.
• Design data and task decomposition strategies to balance compute load.
• Manage a multi-level memory hierarchy and orchestrate DMA transfers.
• Develop and optimize per-core radar kernels using SIMD and intrinsics.
• Build pre-silicon validation platforms for early software development.
• Profile pipelines across cores and optimize for performance and power.

Skills

Multicore software

Partitioning scheduling

C/C++

SIMD

VLIW

DMA

RTOS

Memory hierarchy

Tools

Bare-metal

Job description

At Teradar, we are pioneering a new era in perception with the world’s first automotive terahertz vision sensor, delivering ultra-high-resolution imaging in any weather condition. Founded in Boston, Teradar’s solid-state, chip-scale technology unlocks safer, smarter vehicles and opens the door to transformative applications in mobility, defense, and beyond.

Responsibilities

• Architect and implement multicore software for radar signal processing on an SoC, partitioning pipelines across multiple cores connected by a network-on-chip.
• Design data and task decomposition strategies that balance compute load, minimize inter-core communication, and exploit pipeline, data, and functional parallelism across radar processing stages.
• Manage a multi-level memory hierarchy (core-local, cluster-shared, and SoC-global) - placing buffers, sizing working sets, and orchestrating DMA transfers to sustain high memory throughput and keep cores fed with radar data cubes while hiding stalls behind useful work.
• Develop and optimize per-core radar kernels (FFTs, filters, matrix operations, CFAR variants, MIMO processing) using SIMD, VLIW, fractional arithmetic, and intrinsics.
• Build, use, and maintain pre-silicon validation platforms such as virtual prototypes for early multicore software development, performance projection, and testing.
• Profile end-to-end radar pipelines across cores - identifying load imbalance, NoC contention, memory bandwidth bottlenecks, and synchronization overhead - and iterate on partitioning, scheduling, and data layout to optimize performance, power, and area trade-offs.

Skills & Experience

• Strong experience developing multicore embedded software on an SoC, including workload partitioning, scheduling, and load balancing across cores.
• Hands-on experience managing shared and distributed memory across a multi-level memory hierarchy, including explicit DMA-driven data movement, double/multi-buffering, and techniques for sustaining high memory throughput under real-time constraints.
• Working knowledge of bare-metal programming and/or real-time operating systems, including boot flow, linker scripts, memory maps, interrupt and exception handling, and real-time task scheduling.
• Solid understanding of computer architecture and micro-architecture fundamentals.
• Proficiency in C/C++ along with SIMD and VLIW programming models, intrinsics, and fractional arithmetic applied to radar or DSP kernels.
• Familiarity with radar signal processing concepts - FMCW radar, Range/Doppler/Angle estimation, FFTs, CFAR detection, beamforming, MIMO, and tracking- and the data-flow and bandwidth characteristics they impose on the processing pipeline.
• Exposure to virtual prototypes or pre-silicon validation platforms.
• Ability to analyze and resolve performance bottlenecks spanning compute, memory bandwidth, NoC, and synchronization, and to optimize for PPA across the full multicore radar pipeline.