Distinguished Circuit Engineer
Ampere Computing LLC
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Benefits offered by this job
Job summary
Ampere Computing LLC in Santa Clara, CA seeks a Distinguished Circuit Engineer to lead HSIO/SerDes direction for high-speed interfaces on advanced nodes. You’ll own end-to-end specs, drive in-house IP, and collaborate with vendors and foundries to deliver reliable server SoCs.
You will mentor engineers, influence roadmaps, and ensure robust post-silicon validation and production readiness across Die-to-Die, memory, and peripheral IOs.
Qualifications
- Proven leadership in high-speed SerDes and mixed-signal PHY silicon development.
- Experience taking complex SerDes (PAM4/NRZ, D2D, PCIe, DDR, or UCIe) from concept to high-volume production on advanced nodes.
- Deep expertise in analog/mixed-signal design (TX/RX, PLLs, clocking, equalization) across PVT corners.
- Strong knowledge of high-frequency signaling, PDN, crosstalk, and package parasitics.
- Hands-on post-silicon validation using lab instruments and automated test flows.
- Excellent cross-functional communication and vendor/foundry collaboration.
Responsibilities
- Define the technical roadmap for HSIO/SerDes, IP development, and integration of server SoCs.
- Lead in-house IP design and manage external IP partnerships with vendors and foundries.
- Specify detailed IP electrical, functional, and timing requirements with SoC and packaging teams.
- Guide circuit architectures (analog/mixed-signal) and oversee end-to-end implementation from spec to production.
- Directed post-silicon characterization, debugging, and yield-focused validation.
- Mentor engineers, influence leadership, and align roadmaps across organizations.
Skills
Education
Tools
Job description
Ampere is a semiconductor design company for a new era, leading the future of computing with an innovative approach to CPU design focused on high-performance, energy efficient AIcompute.
As a pioneer in the new frontier of energy efficient high-performance computing, Ampere is part of the Softbank Group of companies driving sustainable computing for AI, Cloud, and edge applications.
Join us at Ampere and work alongside a passionate and growing team-we’dlove to have you apply!
We are seeking a Distinguished Circuit Engineer to lead Ampere’s High-Speed I/O (HSIO) and SerDes technical direction. This role balances two core responsibilities: leading custom in-house IP development and driving technical engagements with third-party IP vendors and foundries.
In this position, you will own the technical roadmap for our high-speed interfaces—including Die-to-Die (D2D), memory, and standard peripheral IOs—on advanced process nodes (3nm, 2nm, and beyond). Working closely with system architects, package design, and validation teams, you will have end-to-end technical responsibility from initial specification through implementation, integration, post-silicon characterization, and high-volume productization.
- In-House IP Development: Architect, specify, and guide the design and execution of proprietary, high-efficiency custom SerDes and D2D PHY macros tailored to Ampere’s system requirements.
- Third-Party IP Partnership: Serve as the primary technical interface with external IP vendors (e.g., PHY providers) and foundries; evaluate vendor offerings, drive custom spec modifications, conduct risk assessments, and lead make-vs-buy decisions.
- End-to-End Spec Definition & Integration: Define detailed IP electrical, functional, and timing specifications in close collaboration with SoC architects, package design, SI/PI, and logic/DV teams to ensure clean integration into server SoCs.
- Circuit Architecture & Design Execution: Guide critical analog and mixed-signal circuit architectures—including TX/RX front-ends, clock generation/distribution (PLLs, reference clocks), equalization (DFE/CTLE), and calibration engines across advanced geometries.
- Post-Silicon Characterization & Debug: Define post-silicon validation, characterization, and lab test methodologies for both in-house and third-party IPs. Lead bring-up, BER analysis, eye-centering, and root-cause debugging for complex silicon/interconnect issues.
- Production Quality & Screening: Partner with product and test engineering (PE/TE) to establish HTOL, PVT validation, and production screening flows to ensure robust yield and reliability in volume manufacturing.
- System & Package Co-Design: Collaborate with packaging (advanced substrates, EMIB/interposers) and SI/PI teams to establish channel operating margins, crosstalk limits, and PDN specifications.
- Technical Mentorship & Influence: Mentor circuit and mixed-signal engineers, establish solid design methodologies, and align technical roadmaps with leadership and cross-functional teams.
- Significant experience in a Principal, Fellow, or Distinguished technical leadership capacity focusing on high-speed SerDes / mixed-signal PHY silicon development.
- Proven Silicon Track Record: Extensive history of successfully taking complex, high-speed SerDes (PAM4/NRZ, D2D, PCIe, DDR, or UCIe) from concept to high-volume production in advanced FinFET/GAA process nodes.
- Deep Mixed-Signal Expertise: Master of analog and mixed-signal design concepts (TX/RX front-ends, PLL/clock generation and distribution, equalizers/DFE, CDR, ADC/DAC-based SerDes) and underlying device physics across PVT corners.
- Signal & Power Integrity Acumen: Strong command of high-frequency transmission line theory, channel loss models, crosstalk, package parasitics, substrate modeling, and power distribution network (PDN) integrity.
- Lab & Production Validation Mastery: Substantial hands‑on experience in high-speed post-silicon validation, lab measurement instruments (real-time/sampling scopes, BERTs, VNAs), and automated test chip bring-up.
- Tooling Proficiency: Deep expertise in industry‑standard EDA environments (Cadence Virtuoso, Spectre/CustomSim, Synopsys PrimeSim/FineSim), along with standard extraction and physical verification flows.
- Strategic Communication & Leadership: Exceptional cross‑functional leadership skills; proven ability to influence executive leadership, align cross‑functional stakeholders, negotiate with external IP/foundry partners, and mentor global engineering teams.
- Electrical or Computer Engineering - Bachelor's degree & 15 years of related experience; or master’s degree & 12 years; or PhD & 8 years
At Ampere we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, cash long-term incentive, and comprehensive benefits. The full base pay range for this role is between $279,500 and $419,500, except in the San Francisco Bay Area where the range is between $293,000 and $440,000.
Our benefits include health, wellness, and financial programs that support employees through every stage of life.
Benefit highlights include:
- Premium medical insurance, dental insurance, vision insurance, as well as income protection and a 401K retirement plan, so that you can feel secure in your health and financial future.
- Unlimited Flextime and 10+ paid holidays so that you can embrace a healthy work-life balance.
- A variety of healthy snacks, energizing espresso, and refreshing drinks to keep you fueled and focused throughout the day.
And there is much more than compensation and benefits. At Ampere, we foster an inclusive culture that empowers our employees to do more and grow more. We are excited to share more about our career opportunities with you through the interview process.
#LI-TC
#LI-Hybrid
We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.
Ampere is a semiconductor design company for a new era, leading the future of computing with an innovative approach to CPU design focused on high-performance, energy efficient AIcompute. As a pioneer in the new frontier of energy efficient high-performance computing, Ampere is part of the Softbank Group of companies driving sustainable computing for AI, Cloud, and edge applications. Join us at Ampere and work alongside a passionate and growing team-we’dlove to have you apply!
We are seeking a Distinguished Circuit Engineer to lead Ampere’s High-Speed I/O (HSIO) and SerDes technical direction. This role balances two core responsibilities: leading custom in-house IP development and driving technical engagements with third-party IP vendors and foundries.
In this position, you will own the technical roadmap for our high-speed interfaces—including Die-to-Die (D2D), memory, and standard peripheral IOs—on advanced process nodes (3nm, 2nm, and beyond). Working closely with system architects, package design, and validation teams, you will have end-to-end technical responsibility from initial specification through implementation, integration, post-silicon characterization, and high-volume productization.
- In-House IP Development: Architect, specify, and guide the design and execution of proprietary, high-efficiency custom SerDes and D2D PHY macros tailored to Ampere’s system requirements.
- Third-Party IP Partnership: Serve as the primary technical interface with external IP vendors (e.g., PHY providers) and foundries; evaluate vendor offerings, drive custom spec modifications, conduct risk assessments, and lead make-vs-buy decisions.
- End-to-End Spec Definition & Integration: Define detailed IP electrical, functional, and timing specifications in close collaboration with SoC architects, package design, SI/PI, and logic/DV teams to ensure clean integration into server SoCs.
- Circuit Architecture & Design Execution: Guide critical analog and mixed-signal circuit architectures—including TX/RX front-ends, clock generation/distribution (PLLs, reference clocks), equalization (DFE/CTLE), and calibration engines across advanced geometries.
- Post-Silicon Characterization & Debug: Define post-silicon validation, characterization, and lab test methodologies for both in-house and third-party IPs. Lead bring-up, BER analysis, eye-centering, and root-cause debugging for complex silicon/interconnect issues.
- Production Quality & Screening: Partner with product and test engineering (PE/TE) to establish HTOL, PVT validation, and production screening flows to ensure robust yield and reliability in volume manufacturing.
- System & Package Co-Design: Collaborate with packaging (advanced substrates, EMIB/interposers) and SI/PI teams to establish channel operating margins, crosstalk limits, and PDN specifications.
- Technical Mentorship & Influence: Mentor circuit and mixed-signal engineers, establish solid design methodologies, and align technical roadmaps with leadership and cross-functional teams.
- Significant experience in a Principal, Fellow, or Distinguished technical leadership capacity focusing on high-speed SerDes / mixed-signal PHY silicon development.
- Proven Silicon Track Record: Extensive history of successfully taking complex, high-speed SerDes (PAM4/NRZ, D2D, PCIe, DDR, or UCIe) from concept to high-volume production in advanced FinFET/GAA process nodes.
- Deep Mixed-Signal Expertise: Master of analog and mixed-signal design concepts (TX/RX front-ends, PLL/clock generation and distribution, equalizers/DFE, CDR, ADC/DAC-based SerDes) and underlying device physics across PVT corners.
- Signal & Power Integrity Acumen: Strong command of high-frequency transmission line theory, channel loss models, crosstalk, package parasitics, substrate modeling, and power distribution network (PDN) integrity.
- Lab & Production Validation Mastery: Substantial hands‑on experience in high-speed post-silicon validation, lab measurement instruments (real-time/sampling scopes, BERTs, VNAs), and automated test chip bring-up.
- Tooling Proficiency: Deep expertise in industry‑standard EDA environments (Cadence Virtuoso, Spectre/CustomSim, Synopsys PrimeSim/FineSim), along with standard extraction and physical verification flows.
- Strategic Communication & Leadership: Exceptional cross‑functional leadership skills; proven ability to influence executive leadership, align cross‑functional stakeholders, negotiate with external IP/foundry partners, and mentor global engineering teams.
- Electrical or Computer Engineering - Bachelor's degree & 15 years of related experience; or master’s degree & 12 years; or PhD & 8 years
At Ampere we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, cash long-term incentive, and comprehensive benefits. The full base pay range for this role is between $279,500 and $419,500, except in the San Francisco Bay Area where the range is between $293,000 and $440,000.
Our benefits include health, wellness, and financial programs that support employees through every stage of life.
Benefit highlights include:
- Premium medical insurance, dental insurance, vision insurance, as well as income protection and a 401K retirement plan, so that you can feel secure in your health and financial future.
- Unlimited Flextime and 10+ paid holidays so that you can embrace a healthy work-life balance.
- A variety of healthy snacks, energizing espresso, and refreshing drinks to keep you fueled and focused throughout the day.
And there is much more than compensation and benefits. At Ampere, we foster an inclusive culture that empowers our employees to do more and grow more. We are excited to share more about our career opportunities with you through the interview process.
#LI-TC
#LI-Hybrid
We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.
Ampere is an inclusive and equal opportunity employer and welcomes applicants from all backgrounds. All qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, religion, age, veteran and/or military status, sex, sexual orientation, gender, gender identity, gender expression, physical or mental disability, or any other basis protected by federal, state or local law.
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