Director - Ultra Low-latency Trading System Architect

Royal Bank of Canada; New York (NY); On-site; USD 180,000 - 260,000; Full time

Job summary

Royal Bank of Canada seeks a Senior Technologist to lead the design and implementation of an ultra-low-latency electronic trading platform, targeting microsecond and sub-microsecond latencies.

You will own the technical strategy, establish engineering standards, and drive architecture across protocol design, FPGA acceleration, kernel-bypass networking, and deterministic recovery. This on-site role collaborates with market data, risk, and venue-integration teams to meet aggressive latency goals.

Job description

What is the opportunity?

We are seeking a Senior Technologist to lead the design and implementation of an ultra-low-latency electronic trading platform targeting microsecond and sub-microsecond latencies. This role requires deep expertise across multiple domains: protocol design, distributed systems, market data infrastructure, hardware acceleration, and operational resilience. The successful candidate will own the technical strategy, establish engineering standards, and ensure the stack meets aggressive latency targets while maintaining deterministic failover capabilities and production reliability.

What will you do?

Architecture & Protocol Design:

Design the foundational messaging layer, evaluating trade-offs between FIX and Simple Binary Encoding (for internal components).

FPGA & Hardware Acceleration Strategy:

Evaluate and architect FPGA-based acceleration for latency-critical paths. This includes market data feed parsing, order matching logic, risk checks, and order routing decisions. You will define which components warrant FPGA implementation based on latency budgets, throughput requirements, and cost trade-offs. You will work with vendors such as Exegy, Redline, et al. and establish FPGA trading components.

Kernel Bypass & OS-Level Optimization:

Architect the system to bypass the kernel network stack entirely using technologies like DPDK (Data Plane Development Kit), Open Onload, or similar kernel-bypass frameworks. You will design interrupt handling, packet batching, and memory management to minimize context switches and system call overhead. You will establish CPU affinity and isolation strategies, including CPU pinning, isolcpus kernel parameter configuration, and NUMA optimization for multi-socket systems.

Sequencer & Event Stream Design:

Architect the sequencer component that creates deterministic, replayable event streams with minimal latency overhead. This includes designing the durability model (persisted to ultra-low-latency storage, replicated over high-speed networks), defining sequence numbering schemes, and establishing how the sequencer handles clock skew, network partitions, and replica synchronization. You must ensure that the sequenced stream enables stateless recovery of replicas without introducing bottlenecks.

Ultra-Low-Latency Market Data Infrastructure:

Design the market data ingestion layer targeting microsecond-scale processing. This includes evaluating direct feeds (multicast feeds from exchanges), FPGA-based feed parsing, and kernel-bypass software processing. You will establish data normalization strategies that minimize CPU overhead and latency.

DMA Engine & Order Management:

Lead design of the Direct Market Access engine targeting sub-ten-microsecond order processing. This includes handling concurrent market data consumption, atomic order state management, and consistent failover with minimal latency impact. You will define the order lifecycle state machine, handle edge cases (partial fills, rejections, venue timeouts), and ensure the engine can replay from the sequenced stream deterministically.

Normalized Order Entry & Venue Integration with Hardware Awareness:

Design the abstraction layer that normalizes venue protocols (NYSE, NASDAQ, etc.), enabling the system to support multiple markets without sacrificing latency. You will define the venue adapter pattern with minimal overhead, establish common order entry contracts, and ensure venue-specific idiosyncrasies are encapsulated.

Risk Enforcement Architecture with Hardware Acceleration:

Design the risk check framework targeting sub-microsecond enforcement. You will define enforcement models (client-level limits, market-access limits, pre-flight validation) and evaluate which checks warrant FPGA acceleration versus software optimization. You will establish how risk checks interact with the order flow, define bypass procedures for emergency scenarios, and ensure risk logic is testable and auditable.

Failover, Replication & Deterministic Recovery at Scale:

Architect the replica management strategy for ultra-low-latency systems, including how DMA Engine replicas are provisioned, synchronized via sequencer replay, and failed over with minimal disruption. You will define consistency models appropriate for trading (strong consistency, eventual consistency, or hybrid approaches) and recovery time objectives measured in milliseconds or less.

Network Infrastructure & Colocation Optimization:

Design the network topology with latency as a primary constraint. This includes evaluating placement in colocations with direct proximity to exchange feeds and liquidity providers, minimizing network hops, and potentially using private fiber leases for critical paths.

Monitoring, Observability & Operational Control at Ultra-Low Latency:

Design the monitoring infrastructure that observes the system without introducing latency or jitter. This includes using hardware performance counters, low-overhead tracing, and out-of-band m