Director, SI/PI

Netpreme; Cambridge (MA); Hybrid; USD 180,000 - 240,000; Full time

Benefits offered by this job

Health insurance

401(k) match

Relocation assistance

Visa sponsorship

Lunch stipend

EV charging

On-site gym

Job summary

Netpreme is seeking a Director to lead Signal Integrity and Power Integrity for our first-generation MPU, spanning from silicon to system. You will own system-level SI/PI architecture, drive design guidelines, and perform end-to-end channel simulations for high-speed serial interfaces and memory subsystems.

You will mentor engineers, influence cross-functional teams, and steer DDR5/LPDDR5/LPDDR6 and related interfaces while collaborating with silicon, package, PCB, and manufacturing groups.

Qualifications

• MS or PhD in Electrical Engineering required.
• 5+ years of direct industry experience required.
• Lead SI/PI architecture and analysis for high-speed interfaces.
• Hands-on lab measurements and correlation with simulations.

Responsibilities

• Develop technical solutions for Signal Integrity and Power Integrity.
• Drive system-level SI/PI architecture and guidelines.
• Perform end-to-end channel simulations for high-speed interfaces and memory subsystems.
• Lead SI/PI analysis and optimization for DDR5, LPDDR5, LPDDR6, and other interfaces.
• Correlate simulations with lab measurements and perform root-cause analysis.
• Collaborate with silicon, package, PCB, architecture, and manufacturing teams.

Skills

SI/PI leadership

System architecture

High-speed signaling

Lab measurements

Python

C++

HFSS

ADS

HSPICE

DDR/LPDDR interfaces

Education

MS or PhD in Electrical Engineering

Tools

ADS

HFSS

HSPICE

Job description

About the Role

We are seeking a Director to drive Signal Integrity, Power Integrity of our first generation MPU. It involves all aspects for SI/PI from silicon to system.

This role will be performed onsite from one of our offices in Santa Clara, CA or Boston, MA.

Essential Duties & Responsibilities

• Responsible for technical solution development for Signal Integrity and Power Integrity.

• Drive system-level SI/PI architecture, design guidelines, and layout recommendations.

• Perform end-to-end channel simulations for high-speed serial interfaces and memory subsystems.

• Lead SI/PI analysis and optimization of DDR5, LPDDR5, LPDDR6, and other high-performance memory interfaces.

• Correlate simulations with lab measurements and drive root-cause analysis of signal and power integrity issues.

• Collaborate with silicon, package, PCB, architecture, and manufacturing teams to resolve complex SI/PI challenges.

• Evaluate future package and PCB technologies to support next-generation FPGA and adaptive computing products

Qualifications

• MS or PhD in Electrical Engineering

• 5+ years of direct industry experience

Preferred Qualifications

• Excellent analytical and problem-solving skills with strong attention to detail.

• Proven ability to independently drive technical decisions and influence engineering direction.

• Strong communication and cross-functional collaboration skills.

• Hands‑on experience performing lab measurements and correlating hardware results to simulation models.

• Deep expertise in Signal Integrity with working knowledge of Power Integrity concepts and methodologies.

• Experience with DDR, LPDDR, or other high-performance memory interfaces.

• Experience with FPGA, adaptive computing, ASIC, networking, datacenter, or high-performance computing platforms.

• Experience with PCB, package, and IC‑level power delivery networks.

• Expertise with SI/PI analysis tools including ADS and HFSS; experience with HSPICE is a plus.

• Strong foundation in electromagnetic theory, transmission lines, and circuit analysis.

• Experience mentoring engineers and driving technical leadership across organizations.

• Experience with programming in Python, C++, Matlab.

Compensation & Benefits

• Competitive salary with performance-based bonus and early‑stage equity grant

• 100% employer‑paid Health, Dental, and Vision coverage for you and your dependents

• 401(k) match with immediate vesting, and access to financial advisors to help you reach your financial goals

• 100% employer‑paid Life, Disability, and AD&D insurance, plus a fitness stipend and wellness & mental health perks

• Generous PTO: 20 vacation days, 15 company holidays (including 3 floating days of your choosing)

• Daily lunch stipend

• Enterprise‑level Claude & ChatGPT access with a generous token budget

• Well‑equipped, sunny offices in Santa Clara, CA & Cambridge, MA with on‑site parking and EV charging; on‑site fitness center in Santa Clara; gym discounts near our Cambridge office

• Visa sponsorship and relocation assistance to one of our office hubs

• A collaborative, continuous‑learning environment with smart, dedicated colleagues building the next generation of high‑performance computing architecture

The Opportunity

• Impact: We are tackling a fundamental challenge at the infrastructure layer: unlocking greater AI capability while dramatically improving efficiency. The work we do here compounds across state‑of‑the‑art AI models, systems, and real‑world applications.

• Timing: Joining now means real ownership of the company and meaningful influence over product direction and execution. You’ll work from first principles, move quickly from insight to execution, and see your contributions directly reflected in what we build.

• Culture: You’ll work alongside a group of people who care deeply about rigor, clarity, and impact. We value thoughtful disagreement, fast learning, and intellectual fearlessness. This is a place where strong ideas shine, curiosity is encouraged, and growth is a daily practice.