Digital Verification Engineer

Snowcap Compute; San Francisco, Northern (CA, KY); Hybrid; USD 130,000 - 200,000; Full time

Benefits offered by this job

Medical, dental, and vision

401(k)

Relocation assistance

Job summary

Snowcap Compute in the San Francisco Bay Area is seeking a Digital Verification Engineer to own UVM testbenches for RTL blocks and the full-chip netlist. You will define functional coverage, write directed and constrained-random tests, and manage the regression infrastructure that runs nightly, collaborating with the Digital Architect and RTL/design teams.

Expect hands-on waveform debugging, root-cause analysis, and a drive to close coverage holes.

Qualifications

• Strong UVM and SystemVerilog verification methodology experience on production silicon that taped out and ran.
• Track record of coverage-driven verification—defining the coverage model, closing it, and defending the closure.

Responsibilities

• Own UVM testbench development for RTL blocks and the full-chip netlist — drivers, monitors, scoreboards, and reference models.
• Define functional coverage goals against the microarchitecture spec, track them, and close holes.
• Write directed and constrained-random tests that exercise SFQ-specific logic behaviors and corner cases.
• Build and own the chip-level simulation environment and the regression infrastructure that runs nightly.
• Drive debug cycles with RTL engineers: find root cause and produce verifiable artifacts.
• File, track, and triage functional bugs through to closure — push back when an RTL fix is a spec problem.
• Apply formal verification where it earns its keep — properties, equivalence, model checking.
• Set the verification methodology and infrastructure standards at Snowcap.

Skills

UVM testbench development

SystemVerilog

Coverage-driven verification

Constrained-random testing

Regression automation

Python/Perl scripting

Tools

Formal verification tools

Job description

# Digital Verification EngineerA bug that escapes verification on a superconducting chip costs a tape-out, not a patch. You will own the UVM environment, coverage model, and regression infrastructure that prove the RTL does what the microarchitecture says — and nothing it does not.TeamDesign VerificationEmploymentFull-timePostedMay 2026Role IDSC-2026-007ApplyScroll to apply01About the RoleSnowcap's chip program runs the standard sequence — architecture, microarchitecture, RTL, verification, layout, sign-off — but verification carries an unusual weight here. The logic family is new, the spec is being written for the first time, and the cost of letting a functional bug through to silicon is measured in months and tape-out dollars, not patches. This role is the quality gate between RTL and implementation. You will develop and execute the UVM environment for block-level and full-chip verification, define and close functional coverage, write the directed and constrained-random tests, and own the regression infrastructure that runs every night. You will work directly with the Digital Architect, Microarchitect, and RTL design engineers in a flat, matrixed organization. You will also be the engineer who shows up with the evidence — coverage reports, failing seeds, waveforms — that says yes this is real, or no this is testbench, before anyone changes RTL. In twelve months, the verification environment you build should be the thing the chip team trusts before tape-out — coverage closed, regressions green for the right reasons, and bugs caught at the level they were introduced. The standards you set for what "verified" means at Snowcap become the standards every future verification engineer inherits.02What You'll Own- Own UVM testbench development for RTL blocks and the full-chip netlist — drivers, monitors, scoreboards, and the reference models the checks rely on. - Define functional coverage goals against the microarchitecture spec, track them, and close the holes — including the ones that exist only because PCL logic behaves differently than CMOS. - Write directed and constrained-random tests that exercise SFQ-specific logic behaviors and the corner cases a CMOS-only testbench would never generate. - Build and own the chip-level simulation environment and the regression infrastructure that runs it — nightly, on every RTL change, and against the right coverage closure criteria. - Drive debug cycles with RTL engineers: find root cause, not just symptom, and produce the artifact (waveform, log, test) that makes the bug fixable. - File, track, and triage functional bugs through to closure — and push back when an "RTL fix" is actually a spec problem the microarchitect needs to resolve. - Apply formal verification where it earns its keep — properties, equivalence, model checking on the blocks where directed and random will not get there alone. - Set the verification methodology and infrastructure standards at Snowcap — testbench architecture, coverage discipline, regression hygiene, and what "signed off for tape-out" actually means.03What We Need to See- Strong UVM and SystemVerilog verification methodology experience on production silicon that taped out and ran. Hobby and academic verification do not meet this bar. - Track record of coverage-driven verification — defining the coverage model, closing it, and being able to argue defensibly that what was closed is the right thing to have closed. - Working experience with formal verification tools and methodology — properties, assertions, and the judgment to know when to reach for formal instead of throwing more random at the problem. - Solid working knowledge of the full chip design flow — RTL, synthesis, STA, and the back-end — and what the implementation team needs the verification environment to deliver. - Strong debugging instincts and the discipline to find root cause before declaring a fix. Symptom-only fixes do not pass at Snowcap. - Scripting proficiency in Python, Perl, or equivalent for testbench, regression, and reporting automation — verification infrastructure work is part of the job, not someone else's.04Ways to Stand Out- Verification experience in timing-sensitive or non-standard logic environments — high-speed custom logic, asynchronous designs, wave-pipelined blocks, or FPGA-emulated systems where conventional CMOS timing assumptions had to be re-derived. - Experience standing up a verification environment from scratch — first testbench, first coverage model, first regression — not just inheriting one. - Background at a silicon team that shipped AI inference, HPC, networking, or comparable production chips, in the verification lead or principal engineer band. - Deep familiarity with formal verification flows — equivalence checking, model checking, and properties on the blocks that need it most. - Emulation, FPGA prototyping, or hardware-accelerated regression experience for full-chip-class verification problems. - Familiarity with superconducting digital logic — PCL, SFQ, AQFP, RSFQ, or related — at any level. We do not require it; we will weight it when we find it. - Open-source verification work, methodology contributions, or publications that show ownership outside the scope of a day job.05The EnvironmentSnowcap is a small, technically elite team building chips on a logic family that has never been verified at production scale. There is no inherited testbench, no inherited coverage model, no methodology document to copy from. You will write them, and the next verification engineer to join builds on what you established. We are a flat, matrixed organization. You will work daily with the architect, microarchitect, RTL designers, and physical design — directly, without layers. When a coverage hole and a microarchitecture choice argue with each other, that conversation happens in the room that day, not three reviews from now. This role is on-site at our San Francisco Bay Area or Jacksonville Metro location. The work is hands-on at the testbench, in waveform debug, and in regression triage. If you need a mature verification organization with established UVM templates and a senior verification lead above you, this is not the right fit. If you have wanted to be the senior verification lead, you are in the right place.06Why SnowcapSnowcap Compute is building the world's first commercial superconducting digital computer. Our chips operate at 4.5 Kelvin on Josephson junction-based PCL logic, consuming a fraction of the power of any CMOS system. We are not improving the existing paradigm — we are replacing it.We are a technically elite, small team at the intersection of quantum physics, cryogenic engineering, and advanced semiconductor manufacturing. Every person on this team has a direct line of sight to the product. The work you do here will be visible, consequential, and unprecedented.07CompensationFull medical, dental, and vision · 401(k) · Relocation assistance available for candidates outside the area. Base salary range is shown in USD, posted in good faith and in compliance with California pay transparency law (SB 1162). The range spans the L1 (new grad) entry floor through the senior individual-contributor band — the offer Snowcap reasonably expects to make depends on the level of the seat being filled, plus experience, skills, and location. Range is exclusive of equity, bonus, and benefits. Range reflects the San Francisco Bay Area market; offers for the same role based in Jacksonville Metro, FL are typically 15–25% lower in line with local market norms. Based in the San Francisco Bay Area or Jacksonville Metro, FL · On-Site.08Equal Employment OpportunitySnowcap is an equal opportunity employer. We do not discriminate on the basis of race, color, religion, sex, national origin, age, disability, veteran status, or any other protected characteristic.## Shape the future with us.Send a brief note on why this role and why now, alongside your resume. If you have work we can point to, include a link. We do not work with external recruiters for this role.Submit Application