Design Verification Engineer – Satellite Modem Systems

Amazon; Austin (TX); On-site; USD 110,000 - 160,000; Full time

Benefits offered by this job

Health insurance

401(k) matching

Paid time off

RSU/Stock units

Job summary

Amazon's Project Kuiper seeks an experienced verification engineer to shape and validate digital chip SOCs for satellite communications. You will craft test plans, develop automated regressions, and validate ASICs in Verilog/SystemVerilog while collaborating with design and systems teams.

A strong Matlab background and 2+ years in verification are expected. Based in Austin, TX, this role offers a pathway to impact a cutting-edge wireless solution within a leading tech company and requires U.S.

Qualifications

• Bachelor's degree in Electrical/Communications Engineering or Computer Science, or equivalent experience.
• 2+ years in verification, preferably in communication systems.
• 2+ years in UVM.
• Master's or Ph.D in Electrical/Communications Engineering preferred.
• Familiarity with Matlab; modem design verification or DV integration experience.

Responsibilities

• Implement a state of the art verification environment for RTL testing against Matlab/C models.
• Develop test plans, write tests, run regressions, collect coverage, report progress.
• Participate in validation of ASIC implementations in Verilog/SystemVerilog.
• Collaborate with design and systems teams for system-level verification using UVM test benches.
• Develop a highly automated regression environment to manage builds and database.

Skills

UVM

RTL verification

Verilog/SystemVerilog

Matlab familiarity

Education

Bachelor's degree in Electrical/Communications Engineering or Computer Science

Master's or Ph.D in Electrical/Communications Engineering

Tools

Verilog/SystemVerilog

Matlab

Job description

Amazon's Project Kuiper seeks an experienced verification engineer to shape and validate digital chip SOCs for satellite communications. You will craft test plans, develop automated regressions, and validate ASICs in Verilog/SystemVerilog while collaborating with design and systems teams.

A strong Matlab background and 2+ years in verification are expected. Based in Austin, TX, this role offers a pathway to impact a cutting-edge wireless solution within a leading tech company and requires U.S.