Design Verification Engineer, Amazon Leo

Amazon; Irvine (CA); On-site; USD 120,000 - 180,000; Full time

Job summary

Amazon Leo’s team seeks a Design Verification Engineer to define and implement digital chip SOCs for communications via LEO satellites and gateways. You will work on modems, high-speed interfaces, embedded processors, and DSP solutions using latest CMOS technologies.

You will develop automated verification environments, write tests, and analyze coverage across pre- and post-silicon stages, collaborating with design and systems teams to ensure robust verification.

Qualifications

• Bachelor's degree in Electrical Engineering or related field.
• 2+ years of UVM, C, SystemC and scripting experience.
• 5+ years in verification preferably in communication systems.

Responsibilities

• Implement a state of the art verification environment for IP, subsystem and SOC to facilitate testing of the DUT against reference models.
• Develop detailed test plans and write tests, run regressions, collect coverage matrices and report progress to the program
• Understand and debug system level communication scenarios on pre silicon and post silicon environments.
• Work with the design and communication systems team and participate in system level verification using test benches constructed using UVM, SystemC and DPI-C
• Develop a highly automated environment to triage regression fails and report issues to stake holders.

Skills

UVM

C

SystemC

scripting

Education

Bachelor's degree in Electrical Engineering

Tools

MATLAB

Job description

Design Verification Engineer, Amazon Leo

Job ID: 10519874 | Amazon Kuiper Manufacturing Enterprises LLC

Amazon Leo is Amazon’s low Earth orbit satellite network. Our mission is to deliver fast, reliable internet connectivity to customers beyond the reach of existing networks. From individual households to schools, hospitals, businesses, and government agencies, Amazon Leo will serve people and organizations operating in locations without reliable connectivity.

The Role:

Be part of Amazon Leo’s sub-team responsible for defining and implementing the digital chip SOCs for communications via Low Earth Orbit satellites and Amazon gateways. This is a unique opportunity to define a groundbreaking wireless solution with few legacy constraints. The team works with customer requirements and wireless system teams to define modems, high-speed interfaces, embedded processors, and DSP solutions in latest CMOS generation technologies.

• Implement a state of the art verification environment for IP, subsystem and SOC to facilitate testing of the DUT against reference models.
• Develop detailed test plans and write tests, run regressions, collect coverage matrices and report progress to the program
• Understand and debug system level communication scenarios on pre silicon and post silicon environments.
• Work with the design and communication systems team and participate in system level verification using test benches constructed using UVM, SystemC and DPI-C
• Develop a highly automated environment to triage regression fails and report issues to stake holders.

Export Control Requirement:

Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum.

Basic Qualifications

• Bachelor's degree in Electrical Engineering or a related field
• 2+ years of UVM, C, System C, and scripting experience
• 5+ years in verification preferably in communication systems

Preferred Qualifications

• Master's or Ph.D degree in Electrical / Communications Engineering
• 7+ years in digital verification, preferably in communication systems
• Proficiency in leveraging AI/LLM tools to accelerate verification workflows including AI-assisted test plan, test case generation, debug, human in loop coverage sign off review.
• Familiarity with Matlab
• Modem design verification experience
• System C or Matlab model : development or DV integration experience
• Familiarity with formal verification techniques