Datacenter AI Workload Performance Engineer

Tenstorrent; Santa Clara (CA); Remote; USD 100,000 - 500,000; Full time

Job summary

Tenstorrent is seeking a Datacenter & Agentic AI Workload Performance Analysis Engineer to shape CPU performance across datacenter and AI workloads. You will bridge hardware and software, profiling real-world workloads, and guiding architectural improvements with engineers across CPU, RTL, compilers, and runtimes.

This remote role is based in North America, welcoming candidates at various experience levels; offers competitive compensation and a path to impact next-generation RISC-V CPUs.

Qualifications

• PhD or equivalent in Computer Engineering, CS, or Electrical Engineering with strong workload characterization, benchmark development, performance analysis, or simulation experience.
• Deep understanding of CPU architecture and RISC-V, including pipelines, speculative execution and vector/SIMD.
• Hands-on experience with profiling and simulation tools such as perf, strace, QEMU, or CPU simulators.
• Strong programming skills in C/C++, Python, Bash, and assembly or intrinsics.
• Solid understanding of OS, virtualization, compilers, runtimes, and GNU/RISC-V ecosystems.

Responsibilities

• Analyze CPU performance on datacenter and AI workloads and translate findings into architectural improvements.
• Work across CPU, RTL, software, and compiler teams to optimize performance.
• Profile, simulate, and correlate workloads with hardware behavior to guide design decisions.
• Communicate technical results clearly to architects and engineers.

Skills

CPU performance analysis

Microarchitecture knowledge

Profiling & simulation

Hardware-software boundary

Technical communication

Education

PhD in Computer Engineering/CS/EE

Tools

Linux perf

strace

QEMU

CPU simulators

Job description

Tenstorrent is seeking a Datacenter & Agentic AI Workload Performance Analysis Engineer to shape CPU performance across datacenter and AI workloads. You will bridge hardware and software, profiling real-world workloads, and guiding architectural improvements with engineers across CPU, RTL, compilers, and runtimes.

This remote role is based in North America, welcoming candidates at various experience levels; offers competitive compensation and a path to impact next-generation RISC-V CPUs.