CPU Performance Architect, Platform Architecture

Apple, Inc.; Santa Clara (CA); On-site; USD 216,000 - 325,000; Full time

Job summary

Apple, Inc. in Santa Clara, CA seeks a CPU Performance Architect to advance CPU and memory subsystem design for iPhone, iPad, Mac, and server products. The role focuses on identifying bottlenecks, evaluating ideas, and collaborating with CPU/SoC teams to drive data-driven performance gains.

Strong C/C++ and scripting skills are required, with extensive microarchitecture experience. Applicants should have advanced degrees and a track record in research environments, with a deep understanding of

Qualifications

• Experience in CPU and SOC architecture.
• Experience with performance simulation environments.
• Object-oriented programming in C/C++.
• Experience in scripting languages such as Perl or Python.
• MS or PhD in Electrical or Computer Engineering or Computer Science.
• Knowledge of memory latency tolerance techniques.
• 20+ years of industry experience.
• Understanding of data structures and algorithms.
• Familiarity with SIMD, vector, or accelerator architectures.
• Experience in a research-driven environment.

Responsibilities

• Push CPU performance through memory subsystem optimization and micro-architecture improvements.
• Identify bottlenecks in single-threaded and multi-threaded workloads and evaluate improvement ideas.
• Model, validate, and correlate ideas with RTL and hardware teams.
• Maintain and improve the simulation environment for data-driven decisions.

Skills

CPU/SOC architecture

Performance simulation

C/C++ (OO)

Python/Perl scripting

Education

MS/PhD in EE/CS

Tools

SIMD / vector architectures

Job description

CPU Performance Architect, Platform Architecture

Santa Clara, California, United States Hardware

The CPU Platform Architecture team is responsible for pushing the boundaries of both single-threaded and multi-threaded CPU performance, to enhance the user experience of many Apple products. The team is composed of experts with deep experience in microarchitecture, ISA definition, performance modeling, power modeling, and workload analysis. We are seeking a highly motivated, innovative, and confident individual to join the CPU Platform Architecture team to help drive advanced exploration for next-generation iPhone, iPad, Mac, and server CPU designs.

As a CPU Performance Architect with a focus on the memory subsystem, you will be part of a team that is defining and optimizing CPU and cache micro-architecture. Working collaboratively, you will seek out areas of the design for improvement by identifying performance bottlenecks and evaluate ideas to address them. You will engage with experienced CPU and SoC designers in micro-architecture and RTL to assess the feasibility of ideas through modeling, refine ideas and model correlation, and seed new ideas. The role requires the analysis of single-threaded and multi-threaded workloads across existing and new product categories to identify bottlenecks and opportunities for improvement. We collaborate as a larger CPU architecture and performance team to maintain and improve the simulation environment to enable data-driven decisions and always look for ways to boost the productivity of the entire team.

Minimum Qualifications

• Experience in CPU and SOC architecture and micro-architecture
• Experience with performance simulation environments
• Object-oriented programming experience in C/C++
• Experience in a scripting language such as Perl or Python

Preferred Qualifications

• Knowledge of memory latency tolerance techniques or other aspects of CPU memory subsystem (i.e. prefetching, caching policies)
• 20+ years of relevant industry experience
• MS or PhD in Electrical or Computer Engineering or Computer Science
• Understanding of common data structures and algorithms
• Familiarity with SIMD, vector, or accelerator architectures
• Familiarity with MP performance
• Comfortable in an environment of uncertainty and able to navigate through ambiguities
• Experience in a research-driven environment

At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $216,200 and $324,800, and your base pay will depend on your skills, qualifications, experience, and location.

Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits

Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant

At Apple, we believe accessibility is a fundamental human right. You’ll find that idea reflected in everything here — in our culture, our benefits and our digital tools. By welcoming as many perspectives as possible, we help you build a career where you feel like you belong. Learn about accessibility in Apple’s workplace Learn about reasonable accommodations for job applicants

Apple accepts applications to this posting on an ongoing basis.