Senior Hardware Engineer

Tech Providers,; San Jose (CA); On-site; USD 120,000 - 180,000; Full time

Job summary

A leading company focused on advanced engineering solutions is seeking a Senior Hardware Engineer with extensive experience in prototyping and HAPS technologies. The ideal candidate will engage in mapping complex SoC designs, establishing robust prototyping systems, and collaborating with cross-functional teams to achieve design objectives. With a strong foundation in FPGA design and relevant technical expertise, this role offers an exciting opportunity to contribute to innovative projects in a dynamic environment.

Qualifications

• 8+ years experience in ASIC or a related field.
• Proficiency in synthesis, place, and route flows for FPGAs.
• Experience in RTL coding using Verilog/System Verilog.

Responsibilities

• Map multi-million gate SoC designs onto prototyping platforms.
• Establish prototyping systems and contribute to defining methodology.
• Collaborate with teams to validate functional and performance objectives.

Skills

HAPS

FPGA Prototyping

Emulation

Education

Bachelor's Degree in Electrical or Computer Engineering

Master's Degree in Electrical or Computer Engineering

Job description

Title: Hardware Engineer (Prototyping/HAPS) Sr
Duration: 12+ Months
Location: San Jose, CA (5 days onsite)
Experience: 8+ years (Relevant)
Must Have Skills:

• HAPS
• FPGA Prototyping
• Emulation

What candidate will Be Doing:

• Map multi-million gate SoC designs onto prototyping platforms, creating design partitions, FPGA builds, and testbenches to simulate FPGA components.
• Establish prototyping systems in the lab and contribute to defining, evolving, and supporting our prototyping methodology.
• Option to engage in block-level RTL design or block or top-level IP integration.
• Collaborate with Software, Design, and Verification teams to validate the functional and performance objectives of the SoC.

What we are looking for:

• Proficient with the entire HAPS flow – not just limited to building images (Must Have)
• Having the experience to setup HAPS systems and triage issues around HAPS bringup (Must Have)
• A Bachelor's Degree in Electrical or Computer Engineering, accompanied by a minimum of 10 years of experience in ASIC or a related field, or a Master's Degree in Electrical or Computer Engineering with at least 8 years of experience in ASIC or a related discipline.
• A comprehensive understanding of FPGA design, with proven expertise in partitioning multi-million gate designs across multiple FPGAs.
• Proficiency in synthesis, place, and route flows for FPGAs.
• An in-depth knowledge of digital design concepts, including Clock Domain Crossing (CDC), Reset Domain Crossing (RDC).
• Demonstrated experience in RTL coding using Verilog/System Verilog and integration of third-party IPs.
• A meticulous and methodical approach to triaging, debugging, and identifying root causes of issues throughout various phases of FPGA development.
• Experience in prototyping Networking System-on-Chips (SoCs) on HAPS or Cadence Z2 or Zebu equivalent prototyping platforms.
• A strong understanding of PCIE, DDR, Ethernet, and Networking Protocols.
• Proficiency in prototyping ARM or RISCV CPUs.
• Exceptional scripting skills using languages such as TCL, Python, or Perl