Compiler Engineer

5V Tech; Austin (TX); On-site; USD 180,000 - 260,000; Full time

Benefits offered by this job

Annual Bonus

RSUs

Health Insurance

401(k)

Job summary

5V Tech in Austin, TX is seeking a Principal Compiler Engineer to set the technical direction of our MLIR-based compiler stack while remaining hands-on in the codebase. You will make architectural decisions, build critical subsystems, and mentor a growing team of senior engineers.

You will work with hardware architects and AI researchers to optimize the ISA, memory hierarchy, and co-design for our custom silicon.

Qualifications

• Hands-on ownership of major subsystems in production compilers.
• Strong C++ and compiler infrastructure expertise.
• Experience with MLIR/LLVM and scalable compiler frameworks.
• Track record shipping compiler work others build on.
• Experience leading technical programs across compiler and hardware teams.

Responsibilities

• Lead the technical direction of the compiler, including model ingestion and code generation.
• Implement performance-critical and correctness-critical components yourself.
• Define MLIR dialects, lowering approaches, and pass pipelines.
• Drive co-design with silicon architects on ISA and memory hierarchy.
• Set testing standards for determinism, correctness, and performance.
• Mentor staff and senior engineers and guide technical growth.

Skills

C++

MLIR/LLVM

Compiler design

System-level programming

Team leadership

Education

Master's degree in Computer Science or Computer Engineering

Tools

MLIR

LLVM

CMake

Job description

• Total Comp: 30% annual Bonus, RSU's, Insurance, 401(k), and more

A global technology company is building an MLIR based compiler and inference stack for its own custom AI silicon, a multi core architecture with dedicated accelerators. Real workloads are already running on the hardware at competitive performance per watt. The small team is now building the general purpose compiler stack around that proof point.

They are hiring a Principal Compiler Engineer to set the technical direction of the compiler stack while staying hands on in the codebase. You will make the key architectural decisions, personally build the subsystems that matter most, and develop a growing team of senior compiler engineers. You will work closely with hardware architects, runtime engineers and AI researchers.

What you will do

• Lead the technical direction of the compiler, covering model ingestion, lowering, tiling, scheduling, memory planning and code generation
• Design and build the most performance critical and correctness critical parts of the compiler yourself
• Work with the team to define the MLIR dialect structure, lowering approach and pass pipelines
• Drive hardware and software co-design with silicon architects, influencing the ISA, memory hierarchy and synchronisation features
• Define team standards for testing, determinism, correctness and performance
• Mentor Staff and Senior engineers and guide the team's technical growth
• Represent compiler engineering in cross team technical and roadmap discussions

What you will bring

• 5 to 15 years of compiler engineering experience, including substantial hands on ownership of major subsystems in production compilers
• Strong C++ skills and deep compiler infrastructure expertise
• Hands on experience at scale with MLIR, LLVM or a comparable production compiler framework
• A track record of shipping compiler work that other engineers build on
• A strong grasp of computer architecture and how compilers exploit hardware features
• Experience leading complex technical programmes across compiler and hardware teams
• Experience mentoring senior engineers and shaping technical decisions at team level
• Master's degree in Computer Science, Computer Engineering or a related field
• Compiler work for AI accelerators, NPUs, GPUs, DSPs or VLIW architectures
• Custom MLIR dialects or hardware specific IRs
• Frontends and model formats such as PyTorch, JAX, ONNX, TensorFlow, StableHLO or XLA
• Static scheduling and software managed memory
• Quantization, mixed precision, fixed point or complex arithmetic
• DMA engines and multi level memory hierarchies
• Co-design for new silicon
• Bare metal or embedded inference environments

This role suits someone who can reason across the whole inference path, from a framework level model down to execution on custom silicon, and who wants to stay close to the code rather than move into pure architecture or management.

Full details on the company will be shared once you're through to the next stage.