CMOS RF Analog Engineer

Interna Furniture Design Ltd.; Aliso Viejo, Northern (CA, KY); Hybrid; USD 120,000 - 180,000; Full time

Job summary

Jariet is expanding its CMOS Analog Design team in California, focusing on high-speed data converters and RF/PLL devices using 14nm CMOS technology. The role covers circuit design, layout support, and post-layout verification across production-ready IP and ASIC developments.

The candidate should have a strong background in analog IC design, with hands-on experience in Cadence tools and a track record in commercial IC teams, ready to work in a challenging, execution-focused environment.

Qualifications

• MS or PhD in Electrical Engineering with a minimum of 6 years experience or BSEE degree with at least 8 years of applicable industry experience.
• Familiarity with Cadence schematic, layout, and simulation tools (Spectre, PSS).
• Experience in a commercial IC development team and IC engineering life cycle.

Responsibilities

• Design and simulate high-speed CMOS analog circuits (>10 GHz).
• Support layout and post-layout validation.
• Validate circuit performance in test facilities.
• Participate in design reviews and debugging across IC teams.

Skills

High-speed CMOS analog

RF/PLL design

Circuit verification

Test validation

Layout collaboration

Education

MS/PhD in Electrical Engineering

BSEE with 8+ years' experience

Tools

Cadence tools

Spectre

PSS

Job description

Date: May 2018Jariet is a mature startup with a large customer base in the aerospace and commercial markets. Our focus is on Digital Microwave, which takes our very high speed 64+ GS/s ADC and DAC data converters and marries them with our digital systems for up and down frequency conversion. We have developed test-chips and use them to demo our stateof-the-art hardware. We are now transitioning to production versions of our IP and ASICs. Our location in Redondo Beach has our test lab and analog AFE design team. In our second office in Aliso Viejo we have the digital and analog data converter team.We are actively searching for highly motivated individuals that enjoy challenging, execution-oriented design work with high performance ADC, DAC, PLL devices. We currently utilize 14nm CMOS technology and are looking at scaling to smaller geometries. Our design team requires engineers capable of assuming a broad range of development responsibilities, including chip design, layout, design verification, and test validation. Candidates must have experience working in commercial analog development teams and executing standard design processes and flows.

CMOS Analog Design:

1. General (motherhood and apple-pie):a. Understand and analyze system level design requirementsb. Review existing publications, literature, conference proceedings to investigate solutions torequirementsc. Work within team to design and simulate viable circuitsd. Support circuit layout and post-layout simulatione. Prepare and participate in design reviewsg. Validate circuit performance in test laboratory facilitiesh. Diagnose problems and formulate rework or redesign solution.

2. Specific design skills in increasing order of need:a. High speed (>10 GHz) CMOS analog/RFb. 10+ GS/s DACc. 20+ GHz VCO and PLLd. 10+ GS/s ADC

Qualification Requirements:

• MS or PhD in Electrical Engineering with a minimum of 6 years experience or BSEE degree with at least 8 years of applicable industry experience
• Familiarity with Cadence schematic, layout, and simulation tools. Spectre, PSS, noise, jitter analysis
• Experience working in a commercial IC development team
• Experience with IC engineering life cycle (system definition, system architecture, simulation, circuit design, reliability, test validation)