Cloud-Scale ML Inference ASIC Designer

Amazon

Cupertino (CA)

On-site

USD 183,000 - 248,000

Full time

14 days+

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Job summary

Amazon’s AWS Utility Computing division is seeking an ASIC Design Engineer to design and optimize custom SoCs, including AWS Inferentia for ML workloads. The role focuses on delivering high-performance RTL, managing clock/DFT and power-area trade-offs, and collaborating across verification, synthesis and back-end teams.

Ideal candidates have deep RTL/VLSI experience, strong debugging skills, and proficiency in SystemVerilog, Python scripting, and design reviews.

Qualifications

Bachelor's degree in Electrical Engineering or a related field.
5+ years in RTL design for SOC.
5+ years of VLSI engineering.
5+ years with code quality tools including: Spyglass, LINT, or CDC.

Responsibilities

Integrate multiple subsystems into top level SOC, ensure correct clock/reset/functional/DFT signal routing.
As a key member of the ASIC design team, you will implement and deliver high performance, area and power efficient RTL to achieve design targets and specifications.
Analyze design, microarchitecture or architecture to make trade-offs based on features, power, performance or area requirements.
Develop micro-architecture, implement SystemVerilog RTL, and deliver synthesis/timing clean design with constraints.
Perform lint and clock domain crossing quality checks on the design.
Work with architects, other designers, verification teams, pre- and post-silicon validation teams, synthesis, timing and back-end teams to accomplish your tasks.