ASIC Power Design Engineer II (Full Time) - United States

Cisco Systems, Inc; San Jose (CA); Vor Ort; USD 140.000 - 190.000; Vollzeit

Zusammenfassung

Cisco Systems, Inc. is seeking a power-optimized ASIC design engineer to contribute to low-power methodologies and RTL-to-physical collaboration on advanced silicon. You will perform multi‑domain power analysis and help drive power-aware optimization across chip blocks and full chips.

The role emphasizes automation using Python, TCL, and Perl, with strong emphasis on Linux environments and modern EDA tools, in a fast-paced hardware team delivering next‑gen Cisco silicon.

Qualifikationen

• Completion within the past 3 years, or current enrollment with expected completion within 12 months, of a Bachelors + 2 years of relevant experience or Master’s degree program + 0 years of relevant experience.
• Strong familiarity with low-power design concepts and techniques (UPF/IEEE 1801, clock gating, multi-voltage domains, power switches, retention cells, leakage vs. dynamic power trade-offs).
• Proficiency with hardware description languages (SystemVerilog / Verilog).
• Scripting capability in TCL, Python, or Perl for EDA tool automation and data parsing.
• Familiarity with Linux/Unix development environment

Aufgaben

• Implement and optimize low-power design methodologies (clock gating, power gating, multi-Vt, dynamic voltage and frequency scaling, and UPF/CPF power intent).
• Perform block- and full-chip-level power analysis and estimation using Synopsys PrimePower across operating modes and corners.
• Collaborate with RTL design and architecture teams to identify power bottlenecks and guide RTL/micro-architectural optimizations.
• Achieve timing closure, signal integrity, and power targets across advanced process nodes (FinFET / GAA).
• Develop and maintain automated design and analysis workflows using Python, TCL, and Perl.
• Participate in post-silicon power and performance validation and correlation against pre-silicon PrimePower models

Kenntnisse

Low-power design

SystemVerilog

Python

TCL

Linux

Ausbildung

Bachelor's degree in ASIC/Power Design

Master's degree in related field

Tools

Design Compiler

Fusion Compiler

PrimeTime

StarRC

IC Validator

Cadence Innovus

Jobbeschreibung

Please note this posting is to advertise potential job opportunities. This exact role may not be open today but could open in the near future. When you apply, a Cisco representative may contact you directly if a relevant position opens. Applications accepted until further notice.

Meet the Team

The Silicon One team creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world.

Your Impact

• Implement and optimize low-power design methodologies (clock gating, power gating, multi-Vt, dynamic voltage and frequency scaling, and UPF/CPF power intent).
• Perform block- and full-chip-level power analysis and estimation using Synopsys PrimePower (PTPX) across various operating modes, PVT corners, and functional activity scenarios (VCD/FSDB/SAIF).
• Collaborate closely with RTL design, architecture teams to identify power bottlenecks and guide RTL/micro-architectural power optimizations.
• Achieve timing closure, signal integrity, and power targets across advanced process nodes (FinFET / GAA).
• Develop and maintain automated design and analysis workflows using Python, TCL, and Perl.
• Participate in post-silicon power and performance validation and correlation against pre-silicon PrimePower models.

Minimum Qualifications

• Completion within the past 3 years, or current enrollment with expected completion within 12 months, of a Bachelors + 2 years of relevant experience or Master’s degree program + 0 years of relevant experience. (Relevant fields include ASIC Design or Power Design.)
• Strong familiarity with low-power design concepts and techniques (UPF/IEEE 1801, clock gating, multi-voltage domains, power switches, retention cells, leakage vs. dynamic power trade-offs).
• Proficiency with hardware description languages (SystemVerilog / Verilog).
• Scripting capability in TCL, Python, or Perl for EDA tool automation and data parsing.
• Familiarity with Linux/Unix development environment

Preferred Qualifications

• Direct experience running activity-driven power analysis using FSDB/VCD/SAIF waveforms generated from gate-level and RTL simulations.
• Experience with industry-standard EDA tools such as Synthesis & P&R: Synopsys Design Compiler, Fusion Compiler, IC Validator, or Cadence Innovus and Timing & Signoff: Synopsys Prime Time / Prime Time-SI, Prime Power, StarRC, Siemens Calibre.
• Experience with power integrity / IR-drop / EM analysis tools (e.g., Ansys RedHawk, Voltus).
• Understanding of sophisticated FinFET/GAA process node design rules and low-power library architectures.
• Excellent problem-solving, partnership, and communication skills within multi-functional teams

Why Cisco?

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you.

Message to applicants applying to work in the U.S. and/or Canada

Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process. U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks.

• Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time.
• 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
• 1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco
• Non-exempt employees receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees
• Exempt employees participate in Cisco’s flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations)
• 80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next
• Additional paid time away may be requested to deal with critical or emergency issues for family members
• Optional 10 paid days per full calendar year to volunteer

Incentive Pay for Sales Roles

• .75% of incentive target for each 1% of revenue attainment up to 50% of quota
• 1.5% of incentive target for each 1% attainment between 50% and 75%
• 1% of incentive target for each 1% of attainment between 75% and 100%
• Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation
• For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target
• Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid

For quota-based sales roles on Cisco’s sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined.

The applicable full salary ranges for this position, by specific state, are listed below

• New York City Metro Area: $125,700.00 - $203,100.00
• Non-Metro New York state & Washington state: $111,700.00 - $180,800.00
• Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements.

Cisconians power the future. We make impact as a team, innovating fast and fearlessly to create meaningful solutions on a large scale. The depth and breadth of our technology doesn't just benefit our customers – it also means limitless opportunities for us to experiment and learn. We understand the power each of our unique backgrounds bring when we work together. Because of that, we have a global network of thinkers, doers, experts, and curious creators who help one another do their life’s best work.