ASIC Physical Design Principal Engineer

020 Cisco Systems, Inc.; San Jose (CA); On-site; USD 251,000 - 363,000; Full time

Benefits offered by this job

Medical, dental and vision insurance

401(k) plan with Cisco matching

Paid parental leave

Disability coverage

Life insurance

Restricted stock units

Paid holidays

Wellness days

Vacation and sick time

Job summary

Cisco Systems, Inc. Common Hardware Group (CHG) is seeking a senior ASIC design professional to lead fullchip floorplanning and signoff across 7nm/5nm tech nodes.

You will collaborate with RTL/DFT, EDA vendors and foundries to optimize performance, area, and power while driving state-of-the-art integration flows. The role emphasizes architecture understanding, IP placement, and hierarchical design with a strong emphasis on clocking and power integrity.

Qualifications

• Bachelor’s degree in Engineering and 15+ years of ASIC related experience.
• Master’s degree in Engineering and 12+ years of ASIC related experience, or PhD in Engineering and 7+ years of ASIC related experience.

Responsibilities

• Understand architecture of the design, IP placement constraints and fullchip floorplan.
• Collaborate with system and package design teams to implement the fullchip floorplan.
• RTL-to-GDSII flow: floorplan, power grid, place & route, timing, signoff.
• Improve design methodology by analyzing tool flows and implementing enhancements.
• Coordinate with RTL, DFT, EDA vendors and tool/flow teams for best-in-class design.

Skills

ASIC design experience

RTL2GDSII flow

Floorplanning

Timing closure

Python

AI design tools

Team collaboration

Education

Bachelor’s degree in Engineering

Master’s degree in Engineering

PhD in Engineering

Tools

Innovus

Tempus

Primetime

Calibre

Redhawk

Voltus

Job description

Meet the Team

The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms—like Silicon One—are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world.

Your Impact

Fullchip Floorplan by understanding the architecture of the design, foundry integration guidelines and IP placement constraints Collaborate with the system and package design teams to understand the requirements and incorporate into the fullchip floorplan Perform hierarchical implementation flow, including partition, pin assignment, clock plan and bump planning; Handson experience with Fullchip clock mesh and Flex-HTree methods RTL-to-GDSII implementation: Floorplan, Power Grid plan, place and route, static timing analysis, power integrity, physical verification and equivalence checks with a focus on performance, power and die size optimization. Analyze existing tool flows and methodologies, identifying efficiency gaps and implementing incremental or transformative enhancements. Work closely with RTL, DFT, implementation, EDA vendors, and tool/flow teams to enable best-in-class design methodology. Proficiency in low-power design methodologies using UPF Work with Foundry and standard cell IP vendors to define the signoff methodologies and validate/adjust them when you receive feedback from Post-Silicon Validation teams Experience in using AI tools to improve productivity

Minimum Qualifications

• Bachelor’s degree in Engineering and 15+ years of ASIC related experience,
• Master’s degree in Engineering and 12+ years of ASIC related experience, or PhD in Engineering and 7+ years of ASIC related experience.
• Experience with RTL2GDSII flow and design tapeouts in 7nnm/5nm/3nm or below process technologies.
• Experience working with EDA tools like Innovus, Tempus/Primetime, Redhawk/Voltus or Calibre/Pegasus.

Preferred Qualifications

• Experience working on Fullchip activities; including floor-planning, power-grid planning, partitioning and pin-assignment.
• Experience with hierarchical design, timing closure, physical design convergence, and power integrity analysis.
• Experience with static timing analysis and concepts, defining timing constraints and exceptions, corners/voltage definitions.
• Experience with custom clock (H-Tree or Mesh) at chip level.
• Experience with Python and usage of AI tools by giving accurate prompts.

Why Cisco?

Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you.

Message to applicants applying to work in the U.S. and/or Canada:

The starting salary range posted for this position is $250,600.00 to $362,600.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits. Individual pay is determined by the candidate’s hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process.

• medical
• dental and vision insurance
• a 401(k) plan with a Cisco matching contribution
• paid parental leave
• short and long-term disability coverage
• basic life insurance
• Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time.
• 10 paid holidays per full calendar year
• plus 1 floating holiday for non-exempt employees
• 1 paid day off for employee’s birthday
• paid year-end holiday shutdown
• 4 paid days off for personal wellness determined by Cisco
• Non-exempt employees receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees.
• Exempt employees participate in Cisco’s flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations)
• 80 hours of sick time off provided on hire date and each January 1st thereafter
• up to 80 hours of unused sick time carried forward from one calendar year to the next
• Additional paid time away may be requested to deal with critical or emergency issues for family members
• Optional 10 paid days per full calendar year to volunteer

Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components, subject to the applicable Cisco plan. For quota-based incentive pay, Cisco typically pays as follows: .75% of incentive target for each 1% of revenue attainment up to 50% of quota; 1.5% of incentive target for each 1% of attainment between 50% and 75%; 1% of incentive target for each 1% of attainment between 75% and 100%; and Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation. For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid.

• New York City Metro Area: $250,600.00 - $416,900.00
• Non-Metro New York state & Washington state: $241,400.00 - $371,000.00

* For quota-based sales roles on Cisco’s sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined.

Cisconians power the future. We make impact as a team, innovating fast and fearlessly to create meaningful solutions on a large scale. The depth and breadth of our technology doesn't just benefit our customers – it also means limitless opportunities for us to experiment and learn. We understand the power each of our unique backgrounds bring when we work together. Because of that, we have a global network of thinkers, doers, experts, and curious creators who help one another do their life’s best work.