ASIC Physical Design Lead

Niobiummicrosystems; Columbus, Dayton, Fayetteville (OH, OH, AR); Hybrid; USD 140,000 - 210,000; Full time

Benefits offered by this job

Equity incentives (ISO)

Employer paid medical insurance

HSA with employer contributions

Dental and vision reimbursement

401(k) with employer match

Flexible work location with remote

Flexible time off

Job summary

Niobium Microsystems is seeking an experienced ASIC Physical Design lead in Columbus, OH to drive end-to-end tapeouts and SoC integration. You will own floorplanning, PnR, CTS, and sign-off, partnering with Architecture, RTL, and Verification teams to deliver high-performance, power-efficient silicon.

Ideal candidates have 8+ years in ASIC Physical Design, hands-on Cadence/Synopsys expertise, and a proven tape-out track record on nodes from 16nm to 3nm.

Qualifications

• BS/MS/PhD in Electrical Engineering or related field.
• 8+ years in ASIC Physical Design with multiple tape-outs on advanced tech nodes (16nm–3nm).
• Hands-on proficiency with Cadence and/or Synopsys PD toolchains.
• Strong RTL-to-GDS flow understanding and SoC integration complexity.
• Ability to translate product requirements into physical design goals, budgets, constraints, deliverables.

Responsibilities

• Own and lead physical design activities from RTL handoff to GDSII delivery.
• Define execution strategy, schedules, design methodology, and quality checkpoints.
• Architect and execute floorplanning for large SoCs; IP integration and power layout.
• Lead PnR and timing closure across corners, voltage domains, and conditions.
• Optimize for Power, Performance, and Area; mitigate congestion and ensure physical integrity.
• Implement CTS, drive skew and clock power optimization; lead sign-off strategy.
• Collaborate with DFT, Packaging, and SI to ensure robust timing and packaging.
• Mentor junior engineers and drive continuous improvement in flows and scripts.

Skills

ASIC PD expertise

Floorplanning

Place & Route

CTS

STA/Timing Closure

Physical verification

UPF

Low power design

RTL-to-GDS flow

Cadence

Synopsys

Education

Electrical Engineering degree

Tools

Cadence PD tools

Synopsys PD tools

Job description

About Niobium

At Niobium Microsystems, we develop high performance microelectronic products to enable the secure collection, processing, and distribution of critical data. We are a trusted partner of government research teams and commercial customers whose solutions require lower power, higher efficiency, and proven security.

Founded as a 2021 spinout from Galois, Inc., a world-class security and computing systems research and development company, our team combines decades of experience in advanced semiconductor design with a record of delivering world class solutions.

About This Role

We are seeking a highly experienced ASIC Physical Design to drive the implementation of complex SoC designs from RTL handoff through tapeout. The ideal candidate has 8+ years of hands‑on experience in advanced node physical implementation, proven ownership of multiple successful tapeouts, and the ability to lead both technically and organizationally.

In this role, you will partner closely with Architecture, RTL Design, Verification, DFT, and Power teams to deliver high-performance, power‑efficient silicon across cutting edge technology nodes.

Responsibilities

End-to-End Physical Implementation Leadership

• Own and lead all physical design activities from RTL handoff, floorplanning, and PnR through final GDSII delivery.
• Define execution strategy, schedules, design methodology, and quality checkpoints for the entire physical design flow.

Floorplanning & SoC Integration

• Architect and execute floorplanning strategies for large, hierarchical SoCs, including:
  • IP integration and macro placement
  • Physical partitioning and hierarchy definition
  • Power grid architecture and clock distribution topology
  • DIE size, aspect ratio, and physical constraints
• Collaborate with Architecture and RTL teams to ensure physical feasibility, timing closure readiness, and area/power targets.

Place & Route + Timing Closure

• Lead block-level and top-level PnR using industry standard EDA tools (Cadence, Synopsys).
• Drive timing convergence across corners, modes, voltage domains, and operating conditions.
• Own optimization for PPA (Power, Performance, Area), congestion mitigation, and physical integrity.

Clocking, Power, and Sign-Off

• Implement CTS and drive skew, latency, and clock power optimization.
• Lead IR/EM sign-off strategy, thermal analysis, and full chip physical verification (DRC/LVS/ERC).
• Integrate and validate low power methodologies, including UPF/CPF flows.

Cross-Functional Collaboration & Quality Ownership

• Partner with DFT and PD teams to ensure scan insertion, BIST structures, and test modes are physically robust and timing clean.
• Work with Packaging and SI teams on bump planning, floorplan constraints, and package-aware timing.
• Set physical design quality standards, conduct design reviews, and ensure flawless execution through tapeout.

Leadership & Mentorship

• Provide technical leadership to a team of junior and mid-level physical designers.
• Mentor, coach, and guide engineers in methodology, debug, and best practices.
• Champion continuous improvement across flows, scripts, and design methodology.

Key Qualifications

Education

• BS/MS/PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field. (Advanced degree preferred for leadership roles.)

Required Technical Expertise

• 8+ years of relevant experience in ASIC Physical Design, with a strong track record of multiple tape‑outs at advanced technology nodes (16nm -> 3nm preferred).
• Deep expertise in:
  • Floorplanning
  • Place & Route
  • CTS
  • STA/Timing Closure
  • Physical verification & sign-off
  • Low power design and UPF
• Strong hands on proficiency with Cadence and/or Synopsys physical design toolchains.
• Solid understanding of RTL-to-GDS flows, design architecture trade‑offs, and SoC integration complexities.
• Ability to translate product requirements into physical design goals, budgets, constraints, and deliverable plans.

Required General Skills

• Strong communication skills—able to articulate technical decisions across cross-functional teams.
• Highly motivated, proactive, and able to operate effectively in a distributed team environment.
• Comfortable owning schedules, deliverables, and quality in a fast‑moving development cycle.
• Exceptional analytical, debugging, and problem‑solving skills with a meticulous attention to detail.

Location

Niobium is headquartered in Columbus, Ohio with additional locations in Fayetteville, Arkansas, Portland, Oregon, and Dayton, Ohio. We will not be limited by geography for the right candidate.

Benefits

Niobium offers a highly competitive benefits program to support employees and their families, including:

• Competitive salaries
• Equity in the form of Incentive Stock Options (ISO)
• Employer paid medical insurance plan
• Health Savings Account (HSA) with employer contributions
• Dental and vision reimbursement account (HRA)
• 401(k) retirement plan with employer match
• Flexible work location with remote options
• Flexible time off