Analog Mixed-Signal IC Design Engineer (Custom Digital Timing Characterization and Liberty Modeling) – TeraWave

Blue Origin LLC; California (MO); Hybrid; USD 230,000 - 323,000; Full time

Benefits offered by this job

Relocation provided

Travel up to 10%

On-site with CA options

Job summary

Blue Origin LLC is seeking a Senior-level Mixed-Signal / Custom Digital IC Designer to develop timing models for custom analog-digital interfaces used in complex ICs. You will collaborate with analog, digital, STA, verification, and physical design teams to ensure accurate representation in timing flows.

Relocation is provided and travel up to 10% is expected. On-site work in San Diego or Cupertino, with a temporary remote work exception while sites are developed.

Qualifications

• Experience in custom IC design and mixed-signal interfaces.
• Strong understanding of CMOS digital design concepts and timing.
• Experience generating Liberty timing models and characterization.

Responsibilities

• Generate and maintain Liberty .lib models for custom interfaces.
• Characterize timing across PVT, slew, and load ranges.
• Model parasitics, transitions, and power in Liberty attributes.
• Validate Liberty models against transistor-level sims and STA.
• Ensure compatibility with PrimeTime, Tempus, and Innovus.
• Develop SPICE testbenches and run simulations across tools.

Skills

Transistor-level design

SPICE simulation

Digital timing

Timing analysis

PVT variation

Scripting

Education

BS or MS in Electrical/Computer Engineering

Tools

Cadence Virtuoso

Spectre

HSPICE

ADE Explorer/Assembler

PrimeTime

Liberty tooling

Job description

Application close date: Applications will be accepted on an ongoing basis until the requisition is closed.

At Blue Origin, we envision millions of people living and working in space for the benefit of Earth. We’re working to develop reusable, safe, and low-cost space vehicles and systems within a culture of safety, collaboration, and inclusion. Join our team of problem solvers as we add new chapters to the history of spaceflight! Blue Origin is pioneering the future of space-based communications with TeraWave, a revolutionary satellite communications network designed to deliver symmetrical data speeds of up to 6 Tbps anywhere on Earth. This multi-orbit constellation will consist of optically interconnected satellites in low Earth orbit (LEO) and medium Earth orbit (MEO), providing enterprise-grade connectivity for critical operations worldwide. We are seeking a Senior-level Mixed-Signal / Custom Digital IC Designer to develop, simulate, characterize, and deliver timing models for custom analog-digital interface circuits. This role is responsible for creating high-quality Liberty .lib timing models and related collateral for custom digital and mixed-signal interface blocks used in complex integrated circuits.

The ideal candidate has strong transistor-level circuit design and simulation experience, deep understanding of digital timing concepts, and hands‑on experience characterizing custom cells or interfaces for setup, hold, clock-to-Q, recovery/removal, pulse-width, propagation delay, slew, load, and PVT variation. This person will work closely with analog designers, digital implementation engineers, STA engineers, verification engineers, and physical design teams to ensure that custom mixed-signal interfaces are accurately represented in digital timing flows. This role is well suited for a designer who is comfortable operating at the boundary between analog/mixed-signal design, custom digital design, static timing analysis, and library characterization.

Special Mentions

• Relocation provided
• Travel expected up to 10% of the time
• Interviews will include a technical assessment
• This role is based on site in San Diego (preferred), CA Or Cupertino, CA; A temporary remote work exception is approved while our San Diego sites are being developed.

Responsibilities

• Generate and maintain Liberty .lib models for custom digital and analog-digital interface circuits: Define and characterize timing arcs including input-to-output delay, clock-to-Q delay, setup and hold constraints, recovery and removal timing, minimum pulse-width constraints, enable/disable timing, tristate or conditional timing arcs, where applicable.
• Characterize timing over relevant PVT corners, input slew ranges, output load ranges, and extracted parasitic conditions
• Model pin capacitance, transition behavior, leakage, dynamic power, and related Liberty attributes as needed.
• Validate generated .lib files against transistor-level simulation results and downstream STA behavior.
• Ensure .lib compatibility with digital implementation and signoff tools such as PrimeTime, Tempus, Innovus, Fusion Compiler, or equivalent.
• Perform SPICE-level characterization: Build, debug, and maintain transistor-level simulation testbenches for custom interface circuits.
• Run SPICE or FastSPICE simulations using tools such as Spectre, HSPICE, Eldo, FineSim, XA, or equivalent.
• Develop measurement methodologies for setup/hold extraction, propagation delay, clock-to-Q delay, transition time, minimum pulse width, recovery/removal checks, and metastability-sensitive timing behavior
• Perform simulation across PVT and parasitic-extracted views.
• Analyze waveform behavior and identify root causes of timing anomalies, non‑monotonicity, race conditions, glitches, contention, or metastable behavior.
• Create automated characterization flows using scripting languages such as Python, Tcl, Perl, shell, or SKILL.
• Cross-functional integration Collaborate with digital design, STA, verification, physical design, and analog/mixed‑signal teams.
• Support integration of custom .lib models into synthesis, place‑and‑route, timing signoff, and verification flows.
• Review STA results to confirm that custom interface timing is represented correctly.
• Work with layout and physical design teams to understand and model parasitic impact.
• Documentation and methodology development Document characterization methodology, simulation conditions, measurement definitions, and modeling assumptions.
• Produce timing characterization reports and validation summaries.
• Define standard practices for custom cell and mixed‑signal interface characterization.
• Create reusable characterization templates, testbenches, and automation infrastructure.
• Mentor junior engineers in custom timing characterization, Liberty modeling, and SPICE‑based validation.

Minimum Qualifications

• BS or MS in Electrical Engineering, Computer Engineering, or related field, with 7+ years of relevant experience.
• Significant experience in custom IC design, mixed‑signal design, standard‑cell characterization, or digital timing methodology.
• Hands‑on experience with transistor‑level simulation using SPICE‑class tools.
• Strong understanding of CMOS digital circuit design, including: Inverters, Combinational logic, Latches, Flip‑flops, Transmission gates, Clocked logic, Reset/set structures.
• Strong understanding of timing concepts including: Setup time, Hold time, Clock‑to‑Q delay, Propagation delay, Slew/load dependence, Recovery/removal timing, Minimum pulse‑width checks.
• Experience generating or validating Liberty .lib files.
• Experience with PVT‑based characterization and corner analysis.
• Ability to analyze SPICE waveforms and debug unexpected circuit behavior.
• Scripting experience in Python, Tcl, Perl, shell, SKILL, or similar.
• Ability to work effectively with analog, digital, verification, STA, and physical design teams.
• Strong communication skills.

Preferred Qualifications

• Experience with Cadence Virtuoso, ADE Explorer/Assembler, Spectre, and related analog/mixed‑signal design tools.
• Experience with library characterization tools such as: Cadence Liberate, Synopsys SiliconSmart, Solido Characterization Suite, custom in‑house characterization flows.
• Experience with STA tools such as: Synopsys PrimeTime, Cadence Tempus.
• Experience with extracted‑netlist simulation using DSPF, SPEF, or post‑layout parasitic views.
• Experience with level shifters, synchronizers, comparators, custom clocking circuits, and clock‑domain‑crossing interfaces.
• Experience modeling circuits with analog‑dependent timing behavior, metastability, hysteresis, or threshold‑crossing behavior.
• Experience in advanced CMOS technology nodes.
• Familiarity with reliability and robustness analysis, including: Aging, EM/IR, Supply noise, Mismatch, Monte Carlo analysis, Local variation.
• Experience creating Verilog, Verilog‑A, SystemVerilog, or specify‑block models to accompany Liberty timing models.
• Familiarity with digital implementation flows including synthesis, place‑and‑route, timing closure, and signoff.

Base Pay Range for: CA applicants is $230,398.00 - $322,556.85. Other site ranges may differ.

Culture Statement

Don’t meet all desired requirements? Studies have shown that some people are less likely to apply to jobs unless they meet every single desired qualification. At Blue Origin, we are dedicated to building an authentic workplace, so if you’re excited about this role but your past experience doesn’t align perfectly with every desired qualification in the job description, we encourage you to apply anyway. You may be just the right candidate for this or other roles.

Export Control Regulations

Applicants for employment at Blue Origin must be a U.S. citizen or national, U.S. permanent resident (i.e. current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum.

Background Check Required for all positions

Blue’s Standard Background Check Required for Certain Job Profiles: Defense Biometric Identification System (DBIDS) background check if at any time the role requires one to be on a military installation. Required for Certain Job Profiles: Drivers who operate Commercial Motor Vehicles with a Gross Vehicle Weight (GVW), Gross Vehicle Weight Rating (GVWR) or combination of power unit and trailer that meets or exceeds 10,001 lbs. and/or transports placardable amounts of hazardous materials by ground in any vehicle on a public road while in commerce, may be subject to additional Federal Motor Carrier Safety Regulations including: Driver Qualification Files, Medical Certification (obtained before onboarding), Road Test, Hours of Service, Drug and Alcohol Testing, vehicle inspection requirements, CDL requirements (if applicable) and hazardous materials transportation/shipping training. Required for certain Job Profiles: Ability to obtain and maintain Merchant Mariner Credential, which includes pre‑employment and random drug testing as well as DOT physical.

Benefits

• Medical, dental, vision, basic and supplemental life insurance, paid parental leave, short and long-term disability, 401(k) with a company match of up to 5%, and an Education Support Program.
• Stock Options for all regular employees (working at least 20 hours/week).
• Paid Time Off: Up to four (4) weeks per year based on weekly scheduled hours, and up to 14 company‑paid holidays.
• Dependent on role type and job level, employees may be eligible for benefits and bonuses based on the company’s intent to reward individual contributions and enable them to share in the company’s results, or other factors at the company’s sole discretion.
• Bonus amounts and eligibility are not guaranteed and subject to change and cancellation. Please check with your recruiter for more details.

Equal Employment Opportunity

Blue Origin is proud to be an Equal Opportunity/Affirmative Action Employer and is committed to attracting, retaining, and developing a highly qualified and dedicated work force. Blue Origin hires and promotes people on the basis of their qualifications, performance, and abilities. We support the establishment and maintenance of a workplace that fosters trust, equality, and teamwork. We provide all qualified applicants for employment and employees with equal opportunities for hire, promotion, and other terms and conditions of employment, regardless of their race, color, religion, sex, sexual orientation, gender identity, national origin/ethnicity, age, physical or mental disability, genetic factors, military/veteran status, or any other status or characteristic protected by federal, state, and/or local law. Blue Origin will consider for employment qualified applicants with criminal histories in a manner consistent with applicable federal, state, and local laws, including the Washington Fair Chance Act, the California Fair Chance Act, the Los Angeles Fair Chance in Hiring Ordinance, and other applicable laws. For more information on “Know Your Rights,” please see here.

Affirmative Action and Disability Accommodation

Applicants wishing to receive information on Blue Origin’s Affidantage Plans, or applicants requiring a reasonable accommodation in order to participate in the application and/or interview process, please contact us at [e-mail]. Please note this is a publicly managed inbox. Please do not include any personal medical information in your request. We’re committed to building the road to space so our children can build the future. We are a mission‑driven company focused on ideas and innovation, and encourage fresh perspectives from bold voices. At Blue, our team is building the future as their unique selves.

Thank you for your interest in working at Blue Origin! Blue Origin was founded with a vision to enable a future where millions of people are living and working in space to benefit Earth. In order to preserve Earth, Blue Origin believes in the need to enable humanity to expand, explore, find new energy and material resources, and move industries that stress Earth into space. Blue Origin believes it has an important role in building a road to space and lowering the cost of getting there. At Blue Origin, we’re working on this today by developing fully reusable launch vehicles and systems that are safe, reliable and affordable. Every launch vehicle is designed for human spaceflight from the beginning and able to ferry payloads to space.

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