Analog IC Design & Verification Engineer (RF/IP Lab)

Skyworks Solutions, Inc; New Buffalo (IA); On-site; USD 91,200 - 177,200; Full time

Benefits offered by this job

Healthcare benefits

401(k) plan

Employee stock purchase plan

Paid time off

Incentive plan

Job summary

Skyworks Solutions, Inc. is seeking an Analog IC Design and Verification Engineer in Cedar Rapids to lead lab testing and verification of analog and RF IP blocks.

You will work with IP design engineers to ensure functionality and reliability of new IP designs and contribute to IP verification in simulation before tape-out. The role involves leading verification, testing across SOI and bulk CMOS processes, developing lab methodologies, and coordinating DOE testing to optimize fuse programming.

Qualifications

• Experience with analog IC test and verification engineering.
• BS + 5 years of experience / MS +3 years of experience in EE or similar field.
• Hands on experience using analog lab equipment.
• Python programming and data analysis.
• Knowledge of statistical analysis and using Jira for project management.

Responsibilities

• Lead the lab testing and evaluation of analog IP including fuses and other OTP/NVM, temperature sensors, LNA bias DACs, NVG charge pumps, MIPI interfaces, SWIPI interfaces.
• Lead the lab testing and evaluation of RF IP, including LNA and switch designs in new technologies.
• Lead the lab testing and evaluation of fuses and other OTP/NVM IPs.
• Verify analog and RF IP designs in simulation.
• Lead the OTP lab verification qualification process to ensure reliability across polysilicon fuses.

Skills

Analog IC testing

Verilog-A modeling

Python programming

Data analysis

Jira usage

Lab equipment

Education

BS in Electrical Engineering

MS in EE

Tools

Cadence Virtuoso

Keysight ADS

Job description

Skyworks Solutions, Inc. is seeking an Analog IC Design and Verification Engineer in Cedar Rapids to lead lab testing and verification of analog and RF IP blocks.

You will work with IP design engineers to ensure functionality and reliability of new IP designs and contribute to IP verification in simulation before tape-out. The role involves leading verification, testing across SOI and bulk CMOS processes, developing lab methodologies, and coordinating DOE testing to optimize fuse programming.