Analog CAD Engineer

ovt; Santa Clara (CA); On-site; USD 110,000 - 145,000; Full time

Job summary

ovt in California, Santa Clara is seeking an Analog CAD Engineer to support and optimize the analog CAD design flow across schematic, layout, simulation and physical verification using Cadence Virtuoso and Calibre tools.

You will work with multiple foundry PDKs, develop scripts to automate workflows, and collaborate with analog designers to troubleshoot tool and flow issues, while maintaining strong English communication and documentation.

Qualifications

• BS/BE in electrical engineering or related field.
• 2+ years of experience in analog CAD development or support.
• Hands-on experience with Cadence Virtuoso or Synopsys Custom Compiler.
• Familiarity with Calibre verification flows and PDKs.

Responsibilities

• Support and optimize analog CAD flows on the Cadence Virtuoso platform (Schematic, Layout, ADE).
• Work with PDKs from multiple foundries to ensure correct setup and improve design efficiency.
• Develop and maintain scripts and automation to streamline analog design workflows.
• Provide support for Calibre verification flows, including DRC, LVS, and PEX rule decks.
• Collaborate with analog designers to troubleshoot tool, flow, and PDK-related issues.

Skills

Analog CAD

Python scripting

English communication

Education

BSEE

Tools

Cadence Virtuoso

Synopsys Custom Compiler

Calibre

PDK handling

Job description

Position Overview:

Support and enhance the Analog CAD design flow across the full custom IC design cycle, including schematic, layout, simulation, and physical verification using Cadence Virtuoso and Calibre tools.

Responsibilities:

• Support and optimize Analog CAD flows on the Cadence Virtuoso platform (Schematic, Layout, ADE)
• Work with PDKs from multiple foundries to ensure correct setup and improve design efficiency
• Develop and maintain scripts and automation to streamline analog design workflows
• Provide support for Calibre verification flows, including DRC, LVS, and PEX rule decks
• Collaborate with analog designers to troubleshoot tool, flow, and PDK-related issues

Requirements:

• BSEE and 2+ years of experience in Analog CAD development or support
• Hands-on experience with Cadence Virtuoso or Synopsys Custom Compiler
• Familiarity with Calibre rule decks and physical verification flows
• Experience enhancing analog design efficiency through flow or automation improvements
• Python, Perl, or other scripting experience is a strong plus
• Experience with multiple PDKs preferred
• Business-level English communication skills

Annual base salary for this role in California, US is expected to be between $110,000 - $145,000. Actual pay will be determined by several factors such as relevant skills and experience, and the pay of employees in a similar role.

EOE/Minorities/Females/Vet/Disability