Analog and RF Layout Engineer

Capgemini; Sunnyvale (CA); On-site; USD 73,000 - 174,000; Full time

Job summary

Capgemini Engineering is seeking an experienced Analog and RF Layout Engineer to develop complex analog and mixed-signal ICs in advanced CMOS FinFET technologies. You will lead layout implementation, perform floorplanning, and collaborate with design and verification teams to ensure successful tape-outs in high-speed data applications.

The role requires 6+ years in analog/RF IC layout, proficiency with Cadence/Mentor/Synopsys tools, and strong knowledge of floorplanning, physical verification,

Qualifications

• Bachelor’s degree in Electrical Engineering or related discipline.
• 6+ years of experience in analog and RF IC layout.
• Experience with high-speed analog and mixed-signal designs in advanced CMOS FinFET technologies.
• Proficiency with Cadence, Mentor Graphics, or Synopsys EDA tools.
• Experience with transceivers, CMOS drivers, high-speed data converters, or PLLs.
• Strong knowledge of floorplanning, routing, chip integration, and physical verification.
• Understanding of thermal-aware layout, electromigration, and advanced physical-design practices.

Responsibilities

• Lead layout implementation for complex analog and RF ICs in advanced CMOS FinFET technologies, including 7nm and below.
• Perform floorplanning, block-level routing, and top-level chip assembly.
• Partner with design, verification, and product engineering teams to support successful tape-outs.
• Optimize layouts for performance, manufacturability, reliability, and silicon quality.
• Apply thermal-aware design and electromigration mitigation techniques.
• Support physical verification, design reviews, and design-rule compliance.

Skills

Analog RF layout

Floorplanning

Physical verification

Thermal-aware design

Electromigration mitigation

Transceivers/high-speed data paths

CMOS FinFET knowledge

High-speed data converters

Education

Bachelor's degree in Electrical Engineering

Tools

Cadence

Mentor Graphics

Synopsys

Job description

# Analog and RF Layout EngineerSanta ClaraApply for this job* Permanent* Experienced Professionals* Products & Systems Engineering* ID 572470-en\\_USAt Capgemini Engineering, the world leader in engineering services, we bring together a global team of engineers, scientists, and architects to help the world’s most innovative companies unleash their potential. From autonomous cars to life-saving robots, our digital and software technology experts think outside the box as they provide unique R&D and engineering services across all industries. Join us for a career full of opportunities. Where you can make a difference. Where no two days are the same. ## LocationThis role is 100% onsite in Sunnyvale, Ca.## About The Job You're ConsideringCapgemini Engineering is seeking an experienced **Analog and RF Layout Engineer** to develop complex analog and mixed-signal integrated circuits in advanced CMOS FinFET technologies. You will collaborate with design and verification teams to deliver high-performance silicon for advanced communications and high-speed data applications.## Your Role* Lead layout implementation for complex analog and RF integrated circuits in advanced CMOS FinFET technologies, including 7nm and below.* Perform floorplanning, block-level routing, and top-level chip assembly.Partner with design, verification, and product engineering teams to support successful tape-outs.* Optimize layouts for performance, manufacturability, reliability, and silicon quality.* Apply thermal-aware design and electromigration mitigation techniques.* Support physical verification, design reviews, and design-rule compliance.## Your Skills and Experience* Bachelor’s degree in Electrical Engineering or a related discipline.* 6+ years of experience in analog and RF IC layout.* Experience with high-speed analog and mixed-signal designs in advanced CMOS FinFET technologies.* Proficiency with Cadence, Mentor Graphics, or Synopsys EDA tools.* Experience with transceivers, CMOS drivers, high-speed data converters, or PLLs.* Strong knowledge of floorplanning, routing, chip integration, and physical verification.* Understanding of thermal-aware layout, electromigration, and advanced physical-design practices.The base compensation range for this role in the posted location is:$73,150 - $174,000.Capgemini provides compensation range information in accordance with applicable national, state, provincial, and local pay transparency laws. The base compensation range listed for this position reflects the minimum and maximum target compensation Capgemini, in good faith, believes it may pay for the role at the time of this posting. This range may be subject to change as permitted by law.The actual compensation offered to any candidate may fall outside of the posted range and will be determined based on multiple factors legally permitted in the applicable jurisdiction.These may include, but are not limited to: Geographic location, Education and qualifications, Certifications and licenses, Relevant experience and skills, Seniority and performance, Market and business consideration, Internal pay equity.It is not typical for candidates to be hired at or near the top of the posted compensation range.In addition to base salary, this role may be eligible for additional compensation such as variable incentives, bonuses, or commissions, depending on the position and applicable laws.**Capgemini offers a comprehensive, non-negotiable benefits package to all regular, full-time employees.** In the U.S. and Canada, available benefits are determined by local policy and eligibility and may include: * Paid time off based on employee grade (A-F), defined by policy: Vacation: 12-25 days, depending on grade, Company paid holidays, Personal Days, Sick Leave* Medical, dental, and vision coverage (or provincial healthcare coordination in Canada)* Retirement savings plans (e.g., 401(k) in the U.S., RRSP in Canada)* Life and disability insurance* Employee assistance programs* Other benefits as provided by local policy and eligibility**Important Notice:** Compensation (including bonuses, commissions, or other forms of incentive pay) is not considered earned, vested, or payable until it becomes due under the terms of applicable plans or agreements and is subject to Capgemini’s discretion, consistent with applicable laws. The Company reserves the right to amend or withdraw compensation programs at any time, within the limits of applicable legislation.**Disclaimers**Capgemini is an Equal Opportunity Employer encouraging inclusion in the workplace. Capgemini also participates in the Partnership Accreditation in Indigenous Relations (PAIR) program which supports meaningful engagement with Indigenous communities across Canada by promoting fairness, accessibility, inclusion and respect. We value the rich cultural heritage and contributions of Indigenous Peoples and actively work to create a welcoming and respectful environment. All qualified applicants will receive consideration for employment without regard to race, national origin, gender identity/expression, age, religion, disability, sexual orientation, genetics, veteran status, marital status or any other characteristic protected by law.This is a general description of the Duties, Responsibilities and Qualifications required for this position. Physical, mental, sensory or environmental demands may be referenced in an attempt to communicate the manner in which this position traditionally is performed. Whenever necessary to provide individuals with disabilities an equal employment opportunity, Capgemini will consider reasonable accommodations that might involve varying job requirements and/or changing the way this job is performed, provided that such accommodation does not pose an undue hardship. Capgemini is committed to providing reasonable accommodation during our recruitment process. If you need assistance or accommodation, please reach out to your recruiting contact.Please be aware that Capgemini may capture your image (video or screenshot) during the interview process and that image may be used for verification, including during the hiring and onboarding process.Click the following link for more information on your rights as an Applicant in the United States. http://www.capgemini.com/resources/equal-employment-opportunity-is-the-law