AI Inference Performance Engineer (Hardware Accelerators)

Positron Corporation; United States; Remote; USD 200,000 - 300,000; Full time

Benefits offered by this job

Health insurance

Remote-first culture

Unlimited PTO

401(k) with company matching

Job summary

Positron AI is seeking an engineer to improve end-to-end LLM inference performance on our FPGA-based Atlas and Titan systems. You will profile, tune, and scale across hardware-accelerated attention, KV cache, and distributed serving stacks, aligning software with silicon capabilities in production workloads.

The role emphasizes cross-layer debugging, measurable improvements, and collaboration to define robust performance gates for the stack.

Qualifications

• Strong C++ and Python, with hands-on profiling and optimization skills.
• Deep memory hierarchy, concurrency, data movement, batching, scheduling and performance measurement knowledge.
• Experience debugging across application, runtime, driver, firmware, and hardware boundaries.
• Experience bringing up software on new silicon and production deployments.
• Interest in AI-accelerated software development and orchestrating subagents to move faster.

Responsibilities

• Profile and optimize latency, throughput, utilization, and efficiency across hardware-accelerated attention and device runtimes.
• Use performance counters, traces, telemetry, and simulations to isolate regressions and validate fixes.
• Develop and optimize distributed inference capabilities and KV cache management.
• Build benchmarks and workload traces to expose bottlenecks in compute, memory, interconnect, and model loading.
• Partner with test engineers to convert findings into regression tests and release gates.
• Influence hardware and software architecture based on measured performance.

Skills

C++

Python

Profiling

Performance optimization

Linux VFIO

Debug across layers

AI accelerators

Tools

Perfetto

Linux perf

eBPF

Profilers & traces

Job description

Positron AI is seeking an engineer to improve end-to-end LLM inference performance on our FPGA-based Atlas and Titan systems. You will profile, tune, and scale across hardware-accelerated attention, KV cache, and distributed serving stacks, aligning software with silicon capabilities in production workloads.

The role emphasizes cross-layer debugging, measurable improvements, and collaboration to define robust performance gates for the stack.