2027 PhD SerDes Optical Transceivers Silicon Design and Architecture Modeling Engineer InternCoop

AMD; Santa Clara (CA); Hybrid; USD 24,000 - 36,000; Full time

Job summary

AMD is seeking a SerDes Silicon Design and Architecture Modeling Engineer Intern/Co-Op in the San Jose/Santa Clara area. You will work on cutting-edge optical transceivers and SerDes technology, collaborating with experienced engineers on impactful projects.

The role targets PhD candidates in ECE or related fields, with strong design and modeling skills, and a passion for high‑speed interconnects. This full‑time internship offers hands-on mentorship, practical tooling experience, and a path to

Qualifications

• PhD student in Electrical Engineering or related field with at least two years of PhD coursework.
• Strong coursework in device physics, circuit/RTL design, DSP, SerDes, or related areas.
• Experience with simulation or modeling tools; ability to conduct technical research.

Responsibilities

• Engage in SerDes optical transceiver silicon design and modeling projects.
• Collaborate with mentors to define objectives and evaluate solutions.
• Document technical findings and present results to the team at term end.
• Gain experience across CAD, modeling environments, and related tooling.

Skills

SerDes design

Optical transceivers

Circuit design

RTL/logic design

Design automation

Modeling

Education

PhD in Electrical Engineering

Tools

CAD tools

Simulation software

Job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology has the power to solve the world's most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.

Whether you're designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward. Join us and, together, we'll advance your career.

As an AMD intern and co-op, you'll be placed at the epicenter of the AI ecosystem, working alongside experts and industry pioneers. You'll do important work, learn new skills, expand your network, and gain real-world experience on projects that impact millions of end-users worldwide. Whether you're an undergrad or a PhD student, your contributions matter-and your experience here will be a launchpad for what comes next.

JOB DETAILS:

• Location: San Jose, CA or Santa Clara,CA
• Onsite/Hybrid: This role requires the student to work full time (40 hours a week), in either a hybrid or onsite work structure throughout the duration of the co-op/intern term
• Duration:
  • Spring/Summer Co-op : January 25, 2027 - August 13, 2027
  • Summer Internship
    • Semester Students: May 24, 2027 - August 13, 2027
    • Quarter Students: June 21, 2027 - September 10, 2027
  • Summer/Fall Co-op
    • Semester Students: May 24, 2027 - December 10, 2027
    • Quarter Students: June 21, 2027 - December 10, 2027

WHAT YOU WILL BE DOING:

We are seeking highly motivated SerDes Optical Transceivers Silicon Design and Architecture Modeling Engineer Intern/Co-Op candidates to join our team. In this role, you will have the opportunity to work alongside experienced engineers on advanced optical transceiver and SerDes technologies while developing technical and research skills in a collaborative environment.

• We will involve you in cutting-edge silicon design and architecture modeling projects related to SerDes optical transceivers.
• You will work closely with mentor engineers to understand technical problem statements, define objectives, and explore potential solutions.
• We will train you to use the required engineering tools, including CAD, AI, software development, and modeling environments needed to support your project work.
• You will research, evaluate, and propose innovative solutions for challenging design and architecture problems, using analytical and simulation-based approaches.
• Your responsibilities will include documenting technical findings, summarizing results, and delivering a final presentation to the engineering team at the end of the internship or co-op term.

WHO WE ARE LOOKING FOR:

• Currently pursuing a PhD degree in Electrical Engineering, Computer Science & Engineering, Mathematics, Physics, or a related technical field, and have completed at least two years of PhD coursework or research.
• Coursework and/or hands‑on research experience in one or more of the following areas: device physics, circuit design, RTL/logic design, design automation, software engineering, RF design, DAC design, ADC design, SerDes design, DSP design, CDR design, PLL design, or clocking circuit design.
• Familiarity with power-efficient and high-performance circuit design methodologies.
• Experience using simulation, modeling, or design tools to analyze and validate engineering designs. (preferred)
• Demonstrated ability to conduct technical research, evaluate alternatives, and apply engineering fundamentals to solve complex problems.
• Interest in advanced communication systems, optical transceivers, mixed-signal circuits, and next-generation high-speed interconnect technologies.

This role is not eligible for visa sponsorship.

Benefits offered are described: AMD benefits at a glance .

AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's "Responsible AI Policy" is available here.

This posting is for an existing vacancy.