2027 Masters ASIC Package Engineering Co-op/Intern

Socket.dev; Santa Clara (CA); Hybrid; USD 39,000 - 55,000; Full time

Benefits offered by this job

AMD Benefits

Paid internship

Job summary

AMD is seeking a highly motivated ASIC Package Engineering intern/co-op in San Jose, CA or Santa Clara. You will work on substrate, interposer, and bump design, verification, and yield analysis to impact AMD products.

You’ll learn packaging processes, evaluate materials, and collaborate with design and test teams to balance performance and cost in a fast-paced AI ecosystem.

Qualifications

• Must be enrolled in a US-based master's program in a relevant engineering field.
• Coursework related to packaging, circuits, or PCB design is a plus.
• Scripting and data analytics experience are encouraged.

Responsibilities

• Assist in packaging design and development tasks for AMD products.
• Support design verification to ensure performance and quality.
• Analyze yield and defects and help improve processes.
• Collaborate with partners to optimize materials for cost and performance.

Skills

Packaging design software

Scripting languages

Semiconductor theory

Power BI

Electrical engineering fundamentals

Education

Master's in Electrical Engineering

Job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believetechnology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMDis shapingthefuture.

Whetheryou’redesigning next-gen processors, enabling AI breakthroughs, orbringing leading edge products to market, every role at AMD contributes to something bigger— technologythat moves the world forward.Join us and, together, we’ll advance your career.

As an AMD intern or co-op, you’ll be placed at the epicenter of the AI ecosystem, working alongside experts and industry pioneers. You’ll do important work, learn new skills, expand your network, and gain real-world experience on projects that impact millions of end-users worldwide. Whether you’re an undergrad or a PhD student, your contributions matter—and your experience here will be a launchpad for what comes next.

JOB DETAILS:

• Location: San Jose, CA or Santa Clara
• Onsite/Hybrid: This role requires the student to work full time (40 hours a week), in either a hybrid or onsite work structure throughout the duration of the co-op/intern term
• Duration:
  • Spring/Summer Co-op: January 25, 2027 – August 13, 2027
  • Summer Internship:
    • Semester Schools:May 24, 2027 - August 13, 2027
    • Quarter Schools: June 21, 2027 – September 10, 2027
  • Summer-Fall Co-op:
    • Semester Schools: May 24, 2027 – December 10, 2027
    • Quarter Schools: June 21, 2027 – December 10, 2027

WHAT YOU WILL BE DOING:

We are seeking a highly motivated ASIC Package Engineering intern/co-op to join our team and work with our team of engineers in bringing new and advanced packaging technology to reality. In this role –

• We will have your involvement in supporting Package design and Package Development Engineers in prioritizing and optimizing new projects
• We will train you to complete substrate, interposer and bump designs for AMD products, test vehicles and probe card substrates
• We will assign you projects related to design verification implementation to ensure design performance, quality and efficiency
• Analyzing yield and defect metrics to ensure design performance and help improve the yield will be part of your responsibilities
• We will encourage you to evaluate, benchmark packaging materials and interact with partners to achieve the most cost-efficient design and materials for the best performance and yield requirements

WHO WE ARE LOOKING FOR

• You are currently enrolled in a US based University in a Masters degree program majoring in Electrical engineering, Engineering Science, Computer Engineering, Mechanical Engineering, Material Science Engineering, or a related field
• If you have knowledge or experience with any of the following technical skills (or related areas) and are enthusiastic about this role, we strongly encourage you to apply –
• Course related to transmission lines and electric circuits
• Package, silicon or PCB design software
• Scripting languages – Perl / Python / SQL
• Semiconductor theory and packaging process/technology.
• Data analytics and data visualization tools like powerBI

This role is not eligible for visa sponsorship.

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.