FPGA Engineer

Baryonic Space; Çankaya; On-site; TRY 450,000 - 750,000; Full time

Benefits offered by this job

Health insurance

Fuel support

Professional development opportunities

Relocation assistance

Job summary

Baryonic Space is seeking an FPGA Engineer to design, implement, and validate FPGA-based CubeSat payload systems. You will work across RTL/IP development, high-speed interfaces, embedded Linux, and PS-PL integration to deliver robust flight-ready architectures.

You will collaborate with RF, DSP, and software teams to ensure deterministic performance under space constraints and participate in verification, validation, and environmental test support.

Qualifications

• 2+ years of professional FPGA development experience (space or high-reliability systems preferred).
• Strong experience with Xilinx Zynq / Zynq Ultrascale+ architecture.
• Experience integrating and debugging complex block designs in Vivado.
• Working knowledge of Yocto/PetaLinux, device trees, and embedded Linux build systems.
• Experience with JESD204B, high-speed transceivers (GTH/GTY), and multi-gigabit data paths.

Responsibilities

• Design and implement FPGA architectures for CubeSat payloads using Xilinx Zynq/Zynq Ultrascale+ MPSoC platforms.
• Develop custom RTL (VHDL/Verilog/SystemVerilog) IP cores and integrate third-party IP.
• Architect data pipelines from high-speed interfaces to memory and processor subsystems with deterministic latency.
• Implement robust supervisory logic (watchdogs, heartbeat monitors, fault recovery state machines).
• Perform timing closure, resource optimization, power budgeting, and constraint management (XDC).
• Design and validate high-speed interfaces (JESD204B, SpaceWire, CANBus/RS-485).
• Develop Yocto/PetaLinux build environments and integrate FPGA fabric with ARM PS-PL.

Skills

FPGA development

Xilinx Zynq / Zynq Ultrascale+

HDL (VHDL/Verilog/SystemVerilog)

Embedded Linux

RTL/IP development

Education

Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field

Tools

Vivado

ILA/VIO

Yocto/PetaLinux tooling

CANBus/SpaceWire interfaces

Job description

We are seeking a FPGA Engineer responsible for designing, implementing, and validating FPGA-based payload systems for CubeSat platforms. This role focuses on making flight-ready FPGA architectures fully functional within a space-qualified system context, including high-speed data paths, embedded processing, interface integration, and robust supervisory architectures.

You will work across the full stack: RTL/IP development, block design integration, high-speed transceivers, embedded Linux (Yocto/PetaLinux), device trees, DMA pipelines, and system validation. The role requires close collaboration with RF, DSP, embedded software, systems, and hardware teams to deliver reliable payload functionality under space constraints (power, thermal, radiation, bandwidth, and reliability).

Responsibilities

• Design and implement FPGA architectures for CubeSat payloads using Xilinx Zynq / Zynq Ultrascale+ MPSoC platforms.
• Develop custom RTL (VHDL/Verilog/SystemVerilog) IP cores and integrate third-party/vendor IP into block designs.
• Architect data pipelines from high-speed interfaces to memory and processor subsystems with deterministic latency and throughput guarantees.
• Implement robust supervisory logic (watchdogs, heartbeat monitors, fault recovery state machines, reset trees).
• Perform timing closure, resource optimization, power budgeting, and constraint management (XDC).

High-Speed Interfaces & Transceivers

• Implement and validate high-speed serial interfaces including: JESD204B, GTH/GTY transceivers, SpaceWire.
• Integrate and debug CANBus and RS-485 interfaces for satellite subsystem communication.
• Perform signal integrity-aware integration in coordination with hardware teams.

Embedded Linux & System Integration

• Develop and maintain Yocto / PetaLinux build environments.
• Configure device trees, bootloaders, kernel modules, and root filesystems.
• Build and manage SDKs and reproducible build systems.
• Integrate FPGA fabric logic with ARM processing system (PS–PL integration).
• Debug boot flows (FSBL/U-Boot/Linux), peripheral drivers, and memory maps.

Data Movement & Memory Architecture

• Design and optimize DMA-based data paths (AXI-DMA and related IP).
• Ensure correct cache coherence between PS and PL domains.
• Implement high-throughput streaming pipelines with proper buffering and backpressure handling.
• Utilize Analog Devices IP cores (e.g., Radio Core, AXI-DMA, JESD framework) effectively and extend when required.

DSP & Algorithm Acceleration

• Translate algorithmic prototypes from Python/C++ into synthesizable HDL implementations.
• Optimize fixed-point representations and validate numerical performance.
• Collaborate with algorithm engineers to balance precision, latency, and resource utilization.

Verification & Validation

• Develop simulation testbenches and hardware-in-the-loop validation workflows.
• Perform on-board debugging using ILA, VIO, and embedded logic analyzers.
• Conduct bring-up and payload validation at bench level and system level.
• Support environmental and qualification test campaigns (thermal-vacuum, vibration, etc.) as required.
• Produce architecture documentation, interface control documents (ICDs), timing/resource reports, and test procedures.
• Collaborate closely with RF, DSP, software, mechanical, and systems engineers.
• Participate in design reviews and contribute to risk assessment and mitigation strategies.

Minimum Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field.
• 2+ years of professional FPGA development experience (space or high-reliability systems preferred).
• Strong experience with Xilinx Zynq / Zynq Ultrascale+architecture.
• Experience integrating and debugging complex block designs in Vivado.
• Working knowledge of Yocto/PetaLinux, device trees, and embedded Linux build systems.
• Experience with JESD204B, high-speed transceivers (GTH/GTY), and multi-gigabit data paths.
• Experience with AXI-based architectures, DMA engines, and cache-coherent memory systems.
• Understanding of supervisory and fault-tolerant digital architectures (watchdogs, reset logic).
• Experience using lab tools (oscilloscope, logic analyzer, protocol analyzers) for bring-up and debugging.

Preferred Qualifications

• Experience with RFSoC platforms and RF data converters.
• Experience with SpaceWire protocol implementation and debugging.
• Familiarity with Analog Devices HDL frameworks and IP cores.
• Experience designing custom IP from scratch for production systems.
• Experience translating high-level algorithmic code (Python/C++) into optimized FPGA implementations.
• Understanding of fixed-point arithmetic, numerical precision trade-offs, and resource/performance optimization.
• Familiarity with CubeSat or small satellite architectures (power constraints, redundancy, radiation considerations).
• Experience with CI/CD for FPGA builds and reproducible toolchains.
• Exposure to space qualification workflows and environmental test support.
• Experience collaborating across hardware, RF, and software teams in multidisciplinary aerospace environments.

Benefits

• Competitive salary and a comprehensive benefits package, including health insurance and fuel support.
• Continued support for candidates currently enrolled in a master's or doctoral program in a related field.
• Opportunities for continuous professional growth and skill development.
• Engage in a collaborative and innovative work environment.
• Enjoy a positive and enriching work environment, situated in a desirable location.