Standard Cell Library Design Engineer

Broadcom; Singapore; On-site; SGD 70,000 - 100,000; Full time

Job summary

A leading technology company in Singapore is looking for an experienced engineer to join their Central Engineering Group. The successful candidate will design and develop standard cell libraries, requiring expertise in digital or mixed-signal circuit design and familiarity with EDA tools. Candidates should have at least 5 years of related experience. Excellent communication skills and teamwork are essential. Only Singapore Citizens or PRs will be considered.

Qualifications

• 5+ years of related experience is preferred, candidates with Master's should have 3+ years.
• Singapore Citizen/PR only.

Responsibilities

• Design standard cells at transistor level.
• Simulate and analyze circuit designs.
• Generate and verify library EDA models.
• Run regression and quality checks on library deliverables.
• Interface with design teams to support their requirements.

Skills

Circuit design knowledge

Cell layout understanding

Knowledge of Verilog and EDA models

Experience with scripting languages (Unix, Perl, TCL, Python)

Education

Bachelor's in Electrical/Electronic or Computer Engineering

Master's degree in related field

PhD in related field

Tools

Virtuoso

Cadence Skill programming

Job description

Job Description:

Broadcom's Central Engineering Group builds the Foundation IP that powers Broadcom's leading silicon product families. In this position, the successful candidate will be part of the team responsible for the design, development and delivery of standard cell library foundation IP

Job Responsibilities:

• Design standard cells at transistor level
• Simulate and analyze circuit designs
• Generate and verify library EDA models
• Run regression and quality checks on library deliverables
• Interface with design teams to support their requirements

Key Requirements:

• Digital or mixed-signal circuit design knowledge
• Understanding of cell layout or physical design
• Understanding of FinFet, RibbonFet/GAA process nodes
• Understanding of verilog, lef, liberty and other industry standard EDA models
• Familiarity with EDA tools used in FE (Extraction, sims, char) and BE (Verification, STA, P&R)
• Experience with .lib syntax including NLDM/CCS/LVF is a plus
• Experience with Virtuoso, Cadence Skill programming, scripting using Unix, Perl, TCL or Python is strongly desired

Qualifications & Experience:

• Bachelor's in Electrical/Electronic or Computer Engineering and 5+ years of related experience / Candidates with Masters and 3+ years of related experience / PhD in related field of studies with no experience
• Singapore Citizen/PR only

Additional Qualifications:

• Excellent written and verbal communication skills
• Collaborate and work within and across teams

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