Staff Physical Design Engineer

AMD; Singapore; On-site; SGD 70,000 - 100,000; Full time

Job summary

A leading semiconductor company in Singapore is seeking a professional focused on physical design for integrated circuits. The role involves developing plans for Design-For-Test, collaborating with various design groups to meet performance targets, and scripting the design flow. Ideal candidates should have experience in ASIC physical design and a Bachelor's or Master's degree in Engineering. This is a unique opportunity to work in a global team and enhance your technical skills.

Responsibilities

• Develop and implement plans for DFT and ensure timing closure.
• Work with design groups to achieve performance requirements.
• Maintain synthesis and timing analysis scripts.
• Communicate with project teams to resolve issues.

Skills

Analyzing log and report files

Excellent communication skills

Strong analytical and problem-solving skills

Team player

Education

Bachelor's or Master's degree in Computer Engineering/Electrical Engineering

Tools

EDA tools

Linux

Windows

Verilog

System Verilog

C

C++

Perl

TCL

Makefile

Shell scripting

Job description

The focus of this role is to plan, build, and execute the physical design of new and existing features for AMD’s IP, resulting in quality database for the final deliveries.

THE PERSON

You have a passion for modern, complex physical design aspects of digital design. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

KEY RESPONSIBILITIES

Develop and implement plans to synthesize, implement Design-For-Test (DFT) and close timing on complex digital integrated circuits.

Work with various design groups across different disciplines (Logic, Circuits, DFT & Layout) to meet timing closure, area, power, and performance requirements.

Design, implement and maintain synthesis, DFT and Static Timing Analysis scripts using best-in-class methodologies.

Analyze log and report files to ensure the tools are getting the required results and make adjustments to the scripts to get the required results within the scheduled milestones.

Communicate regularly with the project teams world-wide to resolve issues and to ensure meeting targeted goals and schedule.

Provide/propose new/enhance synthesis, DFT and STA flow and methodology to reduce the development TAT to meet product requirements.

PREFERRED EXPERIENCE

Proficient in IP level ASIC physical design including hierarchical implementation

Proficient in using physical design RTL2GDS EDA tools and working in Linux and Windows environments

Experienced with Verilog, System Verilog, C, and C++

Automating workflows in a distributedcomputeenvironment.

Good understanding and hands‑on experience in timing constraints development

Scripting language experience: Perl, TCL, Makefile, shell preferred.

Exposure to leadership or mentorship is an asset

ACADEMIC CREDENTIALS

Bachelors or Masters degree in Computer Engineering/Electrical Engineering