Senior Principal SOC Design Engineer

MAXLINEAR ASIA SINGAPORE PRIVATE LIMITED; Singapore; On-site; SGD 120,000 - 160,000; Full time

Job summary

A technology company in Singapore is seeking an experienced front-end design lead with over 12 years in electronics engineering. You will be responsible for integrating complex System on Chips (SoC) and developing high-quality RTL code using best practices. Expertise in VHDL and Verilog, as well as a solid understanding of Micro-architecture, is essential. The role requires strong collaboration skills and the ability to work with cross-functional teams.

Qualifications

• 12+ years of experience in electronics engineering.
• Experience in integrating complex Systems on Chips (SoC).
• Deep knowledge of Network-on-Chip (NoC) and complex Interconnect Systems.

Responsibilities

• Lead front-end design activities for SoC integration.
• Develop reusable RTL Code using Modular Coding Style.
• Collaborate on Timing constraints and Testability.

Skills

VHDL Coding

Verilog Coding

Front End Design

Micro-architecture

Problem Solving

Team Collaboration

Education

Bachelor or Master's in Electronics Engineering

Tools

Spyglass

Real Intent

IP-XACT

Job description

Job Responsibilities

• Lead the front-end design activities for the integration of complex System on Chips
• Pre-silicon RTL Coding of block, IP and top-level SOC Integration
• Develop reusable RTL Code, using Generic and Modular Coding Style
• Contribute to verification plan from specification and in coordination with architects
• Collaborate on Timing constraints, Testability and Insertion of Low Power Structure such as Power gating, Isolation and Retention Sequential Elements
• Own Linting, CDC, RDC and collaborate with Verification Team and Physical Design
• Co-work with Architecture/ Design/Validation/SW teams. Own cross functional micro-architecture and implementation and drive issues to closure

Job Requirements

• Bachelor Degree or Master's in Electronics Engineering with 12+ years of experience
• Expert in VHDL and Verilog Coding, Front End Design using best-in-class methodology and Micro-architecture
• Should have developed Multi-Million gates IP and integrated heterogenous complex SoC, including Analog and Mixed Signal IP
• Participated in Micro-architecture Specification
• Familiar with Hardware-Software Partitioning, Multi-CPU and Multi-Core Architecture
• Deep knowledge and understanding of NoC and multi-layer complex Interconnect Systems
• Solid verification skills in problem solving, constrained random testing and debugging
• Expertise with Code Linting tools and Static Code checker such as Spyglass, Real Intent, etc
• Expertise in IP-XACT, Connectivity Checks, Register Interfaces and RTL Assembly Tools
• Experience of working with ARM and ARM Eco-system, SERDES systems, communication peripherals (UART, I2C, SPI), power management is a plus
• Experience in WiFi/DOCSIS/Ethernet/DSP/DDR is a plus
• Strong team player and communicator

Location: Next to Bendemeer MRT

Interested candidates may submit detailed CV with the following info:

• Current salary, including AWS or Variable Bonus
• Expected salary
• Availability