Senior Engineer, Yield Analysis, NTI

MICRON SEMICONDUCTOR ASIA OPERATIONS PTE. LTD.; Singapore; On-site; SGD 70,000 - 90,000; Full time

Job summary

A leading semiconductor firm in Singapore is seeking a Yield Analysis Engineer for its NAND Technology Department. In this role, you will identify yield issues, collaborate for solutions, and improve product quality. The ideal candidate holds a relevant degree and has 5-7 years of experience in yield analysis and enhancement, along with programming skills. The position involves significant cross-functional collaboration and innovative problem-solving.

Qualifications

• 5 - 7 years of experience within FA, Yield analysis or Yield Enhancement.
• Deep understanding of probe failure mechanism.
• Ability to do electrical bench data collection is desirable.

Responsibilities

• Discover yield issues in NAND development.
• Drive non-standard deep dive statistical analysis.
• Initiate data mining and correlation studies on new issues.
• Collaborate with module owners on technology gaps.
• Develop techniques in data extraction and automation.

Skills

Data analytics

Statistical analysis

Collaboration

Data mining

Problem-solving

Programming (Python, Java, C, C++)

Education

Bachelor Degree or Masters in Electrical and Electronics Engineering, Material Science

Job description

We have an opening for Yield Analysis Engineer for NAND Technology Deparatment in Singapore. We are looking for candidate that is passionate to innovate in data analytics, and curious to ask what, how and why In this role you will be responsible for providing key feedback and direction on yield improvement activity for NAND memory technology! This role requires a high degree of collaboration across virtually all company functions, up to and including the Executive level.

As Yield Analysis Engineer , you will be responsible for developing innovative NAND product technologies, define, and execute various effective actions to enable solutions to improve yield, quality, reliability, and hit key milestones & achieve the required performance within committed timelines.

Your responsibilities will include, but are not limited to, the following:

• Discover yield issues in NAND development and identify unique metric or combination of metrics, such as wafer/dice/tile shading, ECATS or other custom metric for issues quantification
• Interact with process area, process integration, yield, failure analysis, product engineering, design, and layout teams to drive clear definition of yield, cell, CMOS, qual, and reliability issues and pareto and derive improvement actions needed across tech-nodes and designs
• Own and drive non-standard deep dive statistical analysis of inline, probe, cell, and other critical metrics to define issues/problems, enable early inline detection, and improve the product yield and quality. Quantify and track progress on the issue hit hate, line impact, gap to program goal. Quantify yield improvement/downside seen based on process/probe changes
• Initiate data mining and correlation study on new issue seen. Initiate PFA request to identify root cause of yield issue. Perform inline correlation study to establish inline prediction to yield issue. Make yield projections based on expected improvement/downside. Conduct yield trend analysis, identify root causes in process step, conversion, algorithm change, and design, for yield shift
• Continuously develop/re-define inline detection in collaboration with metrology and RDA team
• Identify and define gaps with current test and co-develop (with product, probe, param engineering) unique parametric/probe bins to detect new fail modes as well as validate new program release
• Collaborate with module owners to identify, quantify key module deficiencies/technology gaps, and drive cross‑functional teams to address. Optimize existing layout, conceptualize, and develop innovative solutions to meet product requirements and manufacturability
• Develop and innovate techniques in extracting data from different databases through various query languages and automate through ing to improve work efficiency
• Assist and support the transfer documentation of layout/architecture fundamentals of new technology from R&D to manufacturing fab.

Requirement

• A Bachelor Degree or Masters in Electrical and Electronics Engineering, Material Science
• 5 - 7 years of experience within FA, Yield analysis or Yield Enhancement
• Discover yield issues in NAND development and identify unique metric or combination of metrics, such as wafer/dice/tile shading, ECATS or other custom metric for issues quantification
• Deep understanding of probe failure mechanism, ability to do electrical bench data collection is desirable
• Fluency in Python, Java , C or C++