RTL Design Engineer (ASIC/SOC/Verilog/System Verilog)

HKM HR MANAGEMENT PTE. LTD.; Singapore; On-site; SGD 80,000 - 110,000; Full time

Job summary

A leading technology firm in Singapore is seeking a skilled engineer to lead RTL design and verification for ASIC/SoC products. The ideal candidate will optimize designs for power, performance, and area while mentoring junior engineers. Expertise in Verilog and simulation tools is crucial for success in this role, which offers opportunities for growth and collaboration in a fast-paced environment.

Qualifications

• Minimum 5 years of experience in RTL/SoC/digital design.
• Proficient in pre-layout and post-layout simulation.
• Knowledge of design flow and backend team collaboration.

Responsibilities

• Lead RTL design, simulation, and verification for ASIC/SoC products.
• Integrate and validate IP blocks for system functionality.
• Mentor junior engineers to facilitate growth.

Skills

RTL design

Verilog

SystemVerilog

Digital design

Simulation tools

Power, Performance, Area optimization

Education

Master in Electrical Engineering

Tools

VCS

Verdi

Job description

Responsibilities

• Lead RTL design, simulation, and verification for company ASIC/SoC products, ensuring robustness.
• Integrate and validate IP blocks for seamless system functionality.
• Analyze requirements for Power, Performance, and Area (PPA), optimizing design trade-offs.
• Collaborate with backend team in RTL coding, implementation, and synthesis for successful tapeout.
• Create and maintain reusable IPs for AI/in-memory computing.
• Support Post-Si testing to ensure product functionality and quality.
• Mentor junior engineers to facilitate their professional growth.
• Contribute to design reviews for improved product performance and reliability.
• Stay current on RTL design methodologies for efficiency and quality.
• Collaborate with cross-functional teams for successful product development.

Requirements

• Minimum Master in Electrical Engineering with 5 years of working experience with emphasis on RTL/SoC/digital design.
• Proficient in Verilog and SystemVerilog.
• Proficient in VCS, Verdi, or similar industry-standard tools.
• Skilled in pre-layout and post-layout simulation.
• Knowledgeable about the design flow and collaboration with backend teams.
• Familiar with AMBA APB and AXI protocols.
• Familiar with RISC/Arm or other core architectures.

How to apply

Interested candidates, please submit your resume by clicking on “Quick Apply” or contact [e-mail] for more details.

Please provide following information in the resume for immediate processing

1. Reasons for leaving current and/or last employment
2. Last drawn and/or current salary
3. Expected salary
4. Date of availability and/or Notice Period

All applications will be treated in strictest confidence and only shortlisted candidates will be notified

Wee Wai Dan

EA License No : 03C5391

EA Reg No : R22109628