Research Associate (IC Design)

Nanyang Technological University; Singapore; On-site; SGD 60,000 - 90,000; Full time

Job summary

A prestigious university in Singapore is looking for a highly skilled Research Associate to enhance the RISC-V CVA6 core by integrating Hardware AES and ASCON Accelerators. The successful candidate should hold a Master’s degree in Electrical or Computer Engineering and have proven experience with RISC-V architecture. This role offers the opportunity to work in a dynamic research environment focused on innovation and excellence.

Qualifications

• Proven experience with RISC-V architecture, especially with custom instruction extensions.
• Proficiency in HDL languages and RTL design.
• Ability to extend assemblers and compilers for custom hardware instructions.

Responsibilities

• Integrate a Hardware AES Accelerator and ASCON Lightweight Cryptography Accelerator.
• Define and implement custom RISC-V instructions.
• Conduct simulations to evaluate performance and latency of the accelerators.

Skills

RISC-V architecture

HDL languages (Verilog, VHDL, SystemVerilog)

FPGA development tools

Cryptographic algorithms

Education

Master’s degree in Electrical Engineering or Computer Engineering

Tools

Vivado

Quartus

Job description

School of Electrical and Electronic Engineering is one of the founding Schools of the Nanyang Technological University. Built on a culture of excellence, the School is renowned for its high academic standards and research. With over 3,000 undergraduates students and 1,000 graduate students it is one of the largest EEE schools in the world and ranks 10th in the field of Electrical & Electronic Engineering in the 2024 QS World University Rankings by Subjects.Today, the School has become one of the world’s largest engineering schools that nurtures competent engineers and researchers. Each year, the School graduates over a thousand students who are ready to take on great ambitions and challenges.For more details, please view:We are looking for a highly skilled Research Associate with experience in RISC-V architecture. The successful candidate will be responsible for adding a Hardware AES and ASCON Accelerator to the RISC-V CVA6 core. This role requires deep knowledge of hardware design, cryptographic algorithms, and the RISC-V instruction set architecture (ISA). You will work closely with the AES and ASCON designers in our team to ensure seamless integration and optimal performance of the cryptographic accelerators.**Key Responsibilities:**Design and Implementation:* Integrate a Hardware AES Accelerator and ASCON Lightweight Cryptography Accelerator into the RISC-V CVA6 (Ariane) core.* Implement memory-mapped interfaces or custom instructions for the accelerators to interface with the CVA6 core.* Collaborate on the integration of the accelerators into the core's execution pipeline.RISC-V ISA Extension:* Define and implement custom RISC-V instructions to utilize the AES and ASCON hardware accelerators, if needed.* Modify the RISC-V CVA6 decode and execution stages to handle the new cryptographic instructions.* Work out the toolchain to ensure assembler, compiler, and simulation support for the custom instructions.Verification and Testing:* Conduct simulations to evaluate the performance, latency, and throughput of the accelerators within the CVA6 pipeline.* Work closely with the AES and ASCON accelerator design team to ensure proper testing and debugging of the hardware integration.**Job Requirements:*** Master’s degree in Electrical Engineering, Computer Engineering, or a related field.* Proven experience with RISC-V architecture, especially with custom instruction extensions and pipeline modifications.* Proficiency in HDL languages (Verilog, VHDL, or SystemVerilog) and RTL design.* Proficiency in toolchain modification, including the ability to extend assemblers and compilers (GCC, LLVM) for custom hardware instructions.* Proficiency of FPGA development tools such as Vivado, Quartus, or similar for prototyping.Preferred Additional Skills:* Strong understanding of ASIC/FPGA design flows, including synthesis, place and route, and timing closure.* Experience in cryptography and implementing cryptographic algorithms in hardware (AES, ASCON, etc.).We regret to inform that only shortlisted candidates will be notified.Hiring Institution: NTUNTU is also home to world-class autonomous institutes – the National Institute of Education, S Rajaratnam School of International Studies, Earth Observatory of Singapore, and Singapore Centre for Environmental Life Sciences Engineering – and various leading research centres such as the Nanyang Environment & Water Research Institute (NEWRI) and Energy Research Institute @ NTU (ERI@N).Ranked amongst the world’s top universities by QS, NTU has also been named the world’s top young university for the past seven years. The University’s main campus is frequently listed among the Top 15 most beautiful university campuses in the world and has 57 Green Mark-certified (equivalent to LEED-certified) buildings, of which 95% are certified Green Mark Platinum. Apart from its main campus, NTU also has a campus in Novena, Singapore’s healthcare district.Under the NTU Smart Campus vision, the University harnesses the power of digital technology and tech-enabled solutions to support better learning and living experiences, the discovery of new knowledge, and the sustainability of resources.For more information, visit