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A leading research institution in Singapore is seeking a Postdoctoral Associate to lead PDK development and collaborate on innovative optoelectronic circuit designs. The candidate will have a PhD in a relevant field, extensive experience in semiconductor processes, and be proficient with design tools such as Cadence and Synopsys. This role offers the opportunity to work within a multidisciplinary team on cutting-edge technology that aims to transform photonic applications. Interested applicants should submit a CV, cover letter, and references.
Wafer-Scale Integrated Sensing Devices based on Optoelectronic Metasurfaces (WISDOM) focuses on semiconductor wafer growth and processing for photonic applications.
This program aims to pioneer a wafer-scale integrated platform which seamlessly combines metasurface optics, optoelectronic devices with a focus on light emitting diodes (LEDs) and vertical surface emitting laser arrays (VCSELs), and silicon complementary metal-oxide semiconductor (CMOS) electronics.
Researchers from MIT, NUS, NTU, A*STAR, Stanford University and University of Illinois form a uniquely qualified interdisciplinary team possessing the skills and infrastructure needed to perform the proposed research. WISDOM program will also involve a strong network of industry partners which are committed to development and translation of the WISDOM technology, thereby enabling outcomes from the program to make a direct impact on industrial applications.
The WISDOM IRG at SMART is seeking a qualified candidate for a Postdoctoral Associate position. This position will entail the following technical responsibilities:
Lead and support PDK development, including device compact models, layout components, validation, and documentation for internal and external design users.
Conduct electronic and optoelectronic circuit design, using simulation, layout, and verification tools; collaborate closely with fabrication teams to ensure design-process co-optimization.
Contribute to foundry process design and integration workflows, including process flow definition, design rule development, cross-wafer process optimization, and collaboration with foundry engineers.
Participate in electronic and optoelectronic device testing, including measurement setup development, data acquisition, and analysis of device- and circuit-level performance.
Work with the cleanroom and process teams as needed to support wafer fabrication, characterization, and documentation.
Collaborate with multidisciplinary team members and contribute to publications, reports, and technology transition activities.
PhD in Electrical Engineering, Materials Science, Applied Physics, or a related discipline.
Prior experience in at least one of the following areas is required:
PDK or CAD tool development
Photonic/CMOS circuit design
Semiconductor process integration or foundry process design
Device testing and measurement (electrical, optical, or optoelectronic)
Experience with industry-standard design tools (e.g., Cadence, Synopsys, KLayout, or similar) is highly preferred.
Strong ability to work in a team environment and collaborate across design, fabrication, and characterization teams.
Excellent communication, documentation, and problem-solving skills.
To apply, please visit our website at: https://portal.smart.mit.edu/careers/career-opportunities
Interested applicants are invited to send in their full CV/resume, cover letter and list of three references (to include reference names and contact information). We regret that only shortlisted candidates will be notified.