Physical design Engineer

SVENTL ASIA PACIFIC PTE. LTD.; Singapore; On-site; SGD 70,000 - 100,000; Full time

Job summary

A semiconductor design firm based in Singapore is seeking an experienced engineer to handle tasks from netlist to GDSII at various design levels. Candidates must possess strong expertise in EDA tools like Synopsys ICC/ICC2 and Cadence Innovus. Responsibilities include hierarchical partitioning, implementation of high-performance cores, and ensuring timing closure. Experience with advanced nodes and scripting would be advantageous.

Responsibilities

• Convert netlist to GDSII at various levels of complexity.
• Implement hierarchical partitioning and budgeting of subsystems.
• Design high performance and low power cores.

Skills

Netlist to GDSII

Hierarchical partitioning

Implementation of high performance cores

Node experience (7nm to 28nm)

Timing Signoff

Block level floor planning

Scan chain reordering

CTS expertise

MMMC optimization

TCL scripting

PnR tools experience

Tools

Synopsys ICC/ICC2

Cadence Innovus

Job description

RESPONSIBILITIES:

Netlist to GDSII at block level, Subsystem Level and at Full chip.

• Worked on multiple tapeouts on Netlist to GDSII
• Hierarchical partitioning and budgeting of block-level subsystems.
• Implementation of high performance (HP) cores, low power designs
• Node experience upto 7nm, 10nm, 14nm, 28nm.
• Timing Signoff in loop through STA and ECO cycle at block and at interface.
• Block level floor planning, power planning and IR drop analysis.
• Scan chain reordering / Scan Chain repartitioning
• CTS expertise and clock tree constraints creation for meeting specifications
• MMMC optimization at Block and Sub-System Level
• Timing closure with Crosstalk and AOCV / POCV
• TCL scripting to fundamentally understand tool usage.

MANDATORY EDA SKILLS

• PnR tools such as Synopsys ICC/ICC2 and/or Cadence Innovus