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Inferact is seeking a TPU performance engineer to enhance vLLM's performance on Google TPUs. You will build and optimize backends, while ensuring benchmarks for correctness and efficiency.
We're looking for candidates with a strong background in computer science, hands-on TPU optimization experience, and familiarity with JAX and XLA. The role is based in Singapore, and offers a competitive salary range of S$200,000 to S$400,000 annually, plus a generous benefits package.
Inferact's mission is to grow vLLM as the world's AI inference engine and accelerate AI progress by making inference cheaper and faster. Founded by the creators and core maintainers of vLLM, we sit at the intersection of models and hardware, a position that took years to build.
We're looking for a TPU performance engineer to make vLLM a first‑class inference engine on Google TPUs. You'll build and optimize TPU backends, compiler integrations, runtime paths, and benchmarking infrastructure using JAX, XLA, Pallas, and related tooling so vLLM can deliver frontier inference performance on TPU hardware.
You'll work at the boundary of inference systems, kernels, compilers, and hardware architecture, improving production‑relevant model serving on TPU with clear correctness, latency, and throughput benchmarks. Your work will help make TPU support in vLLM usable, fast, benchmarked, and maintainable.
Minimum qualifications:
Bachelor's degree or equivalent experience in computer science, engineering, systems, machine learning, or similar.
Hands‑on experience building or optimizing TPU workloads using JAX, XLA, Pallas, or related compiler and runtime tooling.
Deep understanding of TPU execution, memory behavior, compilation, and performance constraints for ML workloads.
Experience optimizing ML kernels or inference paths such as attention, GEMM, sampling, KV cache, fused kernels, or backend runtime paths.
Strong performance profiling and benchmarking skills, with the ability to use measurements, compiler artifacts, correctness tests, and reproducible benchmarks to guide optimization work.
Preferred qualifications:
Experience with vLLM, SGLang, TensorRT‑LLM, XLA‑based serving, or other LLM inference systems.
Familiarity with batching, KV cache, decoding, serving tradeoffs, and backend performance constraints in production inference systems.
Experience with compiler technologies such as XLA, MLIR, LLVM, Pallas, or other kernel DSLs, including lowering, fusion, and backend code generation.
Knowledge of quantization methods such as INT8, FP8, mixed precision, or TPU‑specific numeric formats, including accuracy and performance tradeoffs.
Contributed to vLLM, JAX/XLA, Pallas, PyTorch/XLA, compiler projects, or other open‑source ML infrastructure.
Built TPU benchmarking infrastructure or automated performance regression detection for accelerator workloads.
Worked directly with Google TPU ecosystem stakeholders, accelerator platform teams, or early‑access programs to ship backend, compiler, or inference performance improvements.