IC Verification Engineer

ALLCAN INTERNATIONAL PTE. LTD.; Singapore; On-site; SGD 60,000 - 80,000; Full time

Job summary

A technology company based in Singapore is seeking a Verification Engineer to develop and implement verification plans for IP and SoC levels. The ideal candidate will have experience in functional verification of ASICs/SoCs and strong proficiency in SystemVerilog and UVM methodology. Join a collaborative team and contribute to innovative projects in a dynamic environment.

Qualifications

• Bachelor’s or Master’s degree in Electrical/Electronics Engineering, Computer Science, or a related field.
• Solid experience in functional verification of ASICs/SoCs.
• Strong proficiency in SystemVerilog and UVM methodology.

Responsibilities

• Develop and implement comprehensive verification plans for IP and SoC levels.
• Architect and build reusable testbenches and verification environments using UVM.
• Analyze simulation results and debug test failures.

Skills

Functional verification

SystemVerilog

UVM methodology

Debugging skills

Programming in C/C++

Scripting in Python

Education

Bachelor’s or Master’s degree in Electrical/Electronics Engineering

Tools

VCS

Xcelium

Questa

Job description

Responsibilities

• Develop and implement comprehensive verification plans for IP and SoC levels.
• Architect and build reusable testbenches and verification environments using UVM (Universal Verification Methodology).
• Create directed and constrained-random tests to identify design bugs.
• Develop functional coverage and assertion checks to ensure verification completeness.
• Analyze simulation results, debug test failures, and work with design teams to resolve issues.
• Automate verification flows and regressions using scripting languages.
• Support emulation and FPGA prototyping efforts.

Qualifications and Skills

• Bachelor’s or Master’s degree in Electrical/Electronics Engineering, Computer Science, or a related field.
• Solid experience in functional verification of ASICs/SoCs.
• Strong proficiency in SystemVerilog and UVM methodology.
• Experience with verification tools and simulators (e.g., VCS, Xcelium, Questa).
• Programming and scripting skills (e.g., C/C++, Python, Perl, TCL) are highly desirable.
• Knowledge of formal verification techniques is a plus.
• Strong analytical and debug skills with a keen attention to detail.
• Ability to work effectively in a collaborative, cross-functional team.