IC Design Engineer- PNR/STA

AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED; Singapore; On-site; SGD 70,000 - 90,000; Full time

Job summary

A leading semiconductor company in Singapore is seeking an IC Design Engineer specialized in Place and Route and STA. The successful candidate will develop automation flows for digital and mixed-signal circuits, define essential timing constraints, and collaborate across various teams to meet design goals. A bachelor's degree with relevant experience and strong scripting skills in Perl or Python are necessary for this role, which demands strong technical competency and teamwork across multiple geographies.

Qualifications

• 4+ years experience in IC Design, Place and Route, or STA.
• Hands-on experience with synthesis tools and methodologies.
• In-depth knowledge of signal and power floor planning.

Responsibilities

• Develop automation flow for digital/mixed signal blocks.
• Define constraints for complex blocks including BIST.
• Collaborate with teams to resolve timing violations.

Skills

Synthesis

ICC2

Fusion Compiler

Innovus

Prime Time Tools

TCL

Perl

Automation

Power Floor Plan

Timing Closure

Education

B.S Degree

M.S Degree

Tools

Star-RC

PTS

Job description

IC Design Engineer : Place and Route (PNR), STA(Static Timing Analysis)

Broadcom Central Engineering Group is looking for energetic and passionate Place and Route/STA Engineer. The Successful candidate will be responsible to work in one or more domains of Place and Route, STA development for complex Digital IP subsystems, Semi-custom macros across all types of bleeding edge process technologies.

Available Job Responsibilities

• Netlist to GDS2 automation flow development for complex digital/mixed signal blocks using PNR tools like ICC2 or Innovus in advanced technology nodes
• Define the Floor Plan/placement/routing/Timing constraints in ICC for Complex blocks including BIST to achieve correct by construct DRC/LVS and timing closure.
• Interact with the Cross functional team (Synthesis/STA/DNE) to close the loop in timing violations/DRC/LVS.
• Constraints automation to achieve predictable timing closure through automation with minimal ECOs.
• Perform PNR Architectural feasibilities with multiple power Islands with Optimum Utilization, EM, IR
• Develop Fully Automated PNR, STA development flow to close timing to meet broader frequency requirements.

Skill Sets

• Hands on Experience with Synthesis, ICC2, Fusion compiler, Innovus, Prime time tools
• Hands on experience in defining ICC2/Synthesis constraints that meets timing closure needs
• In-depth knowledge of Signal and Power Floor plan with minimal EM/IR violations
• In-depth expertise with all ICC2/STA options to handle de-ratings, Options to reduce cross talk
• Familiarity with ECO implementation, Familiarity with Tools like Tweaker
• Hands on expertise with TCL/PERL to automate the end to end PNR/STA flow.
• Experience to handle a complex Netlist with multiple frequency domains and ICC timing closure.
• Hands on experience in analyzing and correlating STA vs ICC timing reports.
• Complete exposure to Synopsys Timing closure tools; Star-RC, Prime time, PTSI. Exposure to cadence timing closure flow is a big plus
• Strong Automation and scripting skills using Perl/Python to analyze timing/noise reports and drive for swift timing closure.

Additional Traits

• Strong team player with ability to work across multiple geographies
• Strong Technical and Behavioral competency with a Can do attitude in driving complex projects

Qualification

• B.S Degree with minimum of 4+ Years experience in the relevant domain
• M.S Degree with minimum of 2+ Years experience in the relevant domain.