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Broadcom, Inc. is hiring an experienced IC design engineer to work on advanced 7nm/5nm/3nm/2nm processes. You will manage RTL to GDS flows, including placement, clock tree synthesis, routing, and timing analysis, leveraging Synopsys, Cadence, and Siemens toolchains.
This role values knowledge of front-end design, scripting in tcl/bash, and strong Unix/Linux skills, with a minimum of five years in relevant IC design. Equal opportunity employer.
Utilize commercial and in-house EDA tools (e.g. Synopsys, Cadence, Siemens) for the design and implementation of 100 ~ 400 million gate integrated circuits in 7nm/5nm/3nm/2nm process technologies.
Able to handle a full RTL to GDS or Gates to GDS flow, inclusive of all construction stages (e.g. Placement, clock tree synthesis, detailed routing, physical verification, formal verification and timing analysis).
Some knowledge of front end design and synthesis is advantageous.
Proficiency in UNIX/Linux and scripting languages, e.g. tcl, bash.
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.