FPGA Design Engineer

PERSOL; Singapore; On-site; SGD 60,000 - 80,000; Full time

Job summary

A leading engineering firm in Singapore is seeking an experienced engineer to develop and verify FPGA designs using Vivado and Vitis. Candidates should have a diploma or degree in Engineering, experience with embedded Linux, and proficiency in RTL coding. This role involves working on FPGA-based systems and collaborating with cross-functional teams for design validation.

Qualifications

• Minimum diploma or degree in Engineering.
• Experience with embedded Linux or driver development required.
• Proficiency in RTL coding and verification is a must.

Responsibilities

• Develop and verify RTL designs using Vivado and Vitis.
• Integrate and debug FPGA-based systems.
• Collaborate to validate designs on evaluation boards.

Skills

Embedded Linux

FPGA design tools

RTL coding

Hardware testing

Low-level debugging

Bare-metal C firmware

Education

Diploma/Degree in Engineering

Tools

Vivado

Vitis

Job description

Responsibilities

• Develop, simulate, and verify RTL designs for using Vivado and Vitis.
• Work on FPGA-based system bring-up, integration, and low-level debugging.
• Develop bare-metal C firmware for IP validation and board-level testing.
• Collaborate with cross-functional teams to validate designs on evaluation boards.
• Contribute to hardware platform bring-up, troubleshooting, and performance optimization.
• Support projects involving Versal ACAP and Zynq UltraScale+ MPSoC architectures.

Requirements

• Diploma/Degree in Engineering
• Experience with embedded Linux or driver development
• Proven experience with FPGA design tools (Vivado, Vitis)
• Strong proficiency in RTL coding, verification, and validation (VHDL/Verilog/SystemVerilog)
• Hands‑on experience with FPGA evaluation boards and hardware testing
• Experience with bare‑metal C firmware development for FPGA IP testing and integration
• In‑depth understanding of hardware bring‑up and low‑level debugging techniques
• Familiarity with Versal ACAP and Zynq UltraScale+ MPSoC platforms

We regret to inform that only shortlisted candidates will be notified.