Engineer/ Senior Engineer / Staff Engineer (Design Verification)

PERSOL SINGAPORE PTE. LTD.; Singapore; On-site; SGD 80,000 - 100,000; Full time

Job summary

A technology consulting firm in Singapore is looking for candidates for future openings in verification engineering roles. Responsibilities include developing test plans and verification environments, implementing functional coverage methods, and hands-on debugging with relevant tools. Ideal candidates should have a degree in Electrical Engineering and experience in IC/ASIC design verification, especially with System Verilog and UVM. Strong UNIX scripting skills and teamwork abilities are essential.

Qualifications

• Experience on SOC, Ethernet, PCIe, DDR, USB, ARM CPU.
• Experience in Low Power and formal verification is a plus.
• Fast learner and a good team player.

Responsibilities

• Develop and review test plans.
• Develop verification environment/testbench.
• Implement test with randomization-based methodology.
• Hands-on code/debug with UVM and System Verilog.

Skills

IC/ASIC design verification experience

Debugging ability on System Verilog/UVM

UNIX scripting with Python, Perl

Low Power verification

Education

Bachelor's/Master's Degree in Electrical & Electronics Engineering/Computer/IC design/equivalent

Tools

Synopsys Simulator

Cadence Simulator

Mentor Simulator

Job description

Important Note:

This advertisement is not for immediate hiring but is intended to identify suitable candidates for future openings in this position.

Responsibilities

• Develop and review test plans.


• Develop verification environment/testbench in Module/IP/SOC level.


• Develop verification IP and reference model.


• Implement test with randomization-based coverage driven verification methodology.


• Implement functional and functional/code coverage closure.


• Hands‑on code/debug with UVM, System Verilog, Verilog and SystemC.


• Low Power verification.


• Verification automation flow.

Job Requirements

• Bachelor's/Master's Degree in Electrical & Electronics Engineering/Computer/IC design/equivalent.


• With IC/ASIC design verification experience on SOC, Ethernet, PCIe, DDR, USB, ARM CPU.


• Strong experience and debugging ability on System Verilog/UVM.


• Skilled in Synopsys/Cadence/Mentor Simulator and debugging flow.


• Experience on Low Power and formal verification is a plus.


• Strong in UNIX scripting with Python, Perl, makefile Cshell.


• Fast learner and a good team player.


• Candidates with more years of experience will be considered for a more senior role.

EA License No. 01C4394 • RCB No. 200007268E •EA Registration No. R22109454 Malcolm Lee Jun Hao

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