Design Verification Engineer

BLACK SESAME TECHNOLOGIES (SINGAPORE) PTE. LTD.; Singapore; On-site; SGD 100,000 - 125,000; Full time

Job summary

A technology company in Singapore is seeking an Engineer for Design Verification to work on next-generation automotive SoCs. In this role, you will develop verification platforms using SystemVerilog and UVM, implement Formal Property Verification, and analyze coverage to ensure high functional and quality standards. Ideal candidates possess a Master's or PhD in relevant fields, with strong analytical skills and a collaborative mindset. This position is suitable for both experienced candidates and fresh graduates with relevant coursework.

Qualifications

• Open to fresh graduates with relevant coursework or research experience.
• Internship or project experience in chip design/verification preferred.

Responsibilities

• Develop verification platforms and test cases using SystemVerilog and UVM.
• Promote and implement Formal Property Verification for design modules.
• Perform RTL and gate-level simulation, execute regression tests.
• Analyze code and functional coverage to identify gaps.
• Contribute ideas to enhance verification methodologies.

Skills

Proficiency in SystemVerilog

Scripting languages (Python, Perl, Shell)

Strong analytical and debugging skills

Teamwork and communication skills

Education

Master’s or PhD degree in Electrical Engineering, Computer Engineering, Computer Science

Job description

Position Overview

Black Sesame Technologies is seeking motivated and detail-oriented individuals to join our team as Engineer, Design Verification. This is a great opportunity to be part of a fast-paced environment working on next-generation automotive SoCs. You will be involved in developing industry-grade verification platforms and methodologies to ensure our chips meet the highest functional and quality standards. We're looking for candidates who are curious, self-driven, and passionate about hardware verification.

Responsibilities

• Develop verification platforms and test cases using SystemVerilog and UVM based on verification plans.
• Promote and implement Formal Property Verification (FPV) for relevant design modules.
• Perform RTL and gate-level simulation, execute regression tests, and debug failures.
• Analyze code and functional coverage to identify and close coverage gaps.
• Contribute ideas and improvements to enhance verification methodologies and processes.

Qualification/ Requirements

• Education: Master’s or PhD degree in Electrical Engineering, Computer Engineering, Computer Science, or related fields.
• Experience: Internship or project experience in chip design/verification preferred. Open to fresh graduates with relevant coursework or research experience.
• Programming Skills: Proficiency in SystemVerilog and scripting languages such as Python, Perl, or Shell.
• Problem-Solving: Strong analytical and debugging skills; ability to work through complex technical challenges.
• Teamwork: Collaborative mindset with strong communication skills and willingness to learn in a fast-paced team environment.