Senior Verification Engineer

Synaptics; Katowice; On-site; PLN 253,000 - 339,000; Full time

Job summary

A technology company in Poland is seeking a Senior Verification Engineer to join their SoC Verification team. The role focuses on developing System Verilog UVM testbenches and end-to-end ownership of complex SoCs and IPs verification. Candidates should have 5+ years of experience, strong proficiency in System Verilog and UVM, and excellent communication skills. The position offers competitive benefits including private medical care and costs related to sports activities and language classes.

Benefits

Sharing the costs of sports activities

Private medical care

Sharing the costs of foreign language classes

Qualifications

• 5+ years of experience in SoC verification.
• Strong proficiency in System Verilog and UVM.
• Good understanding of assertion-based verification methodologies.

Responsibilities

• Develop System Verilog UVM testbenches.
• Define and implement a functional coverage model.
• Contribute to the verification strategy and architecture of SoC testbenches.

Skills

System Verilog

UVM

Simulation & debugging tools

Scripting languages (Python, Perl, Tcl)

Versioning tools (GIT)

C / C++ (for embedded CPU verification)

Problem-solving skills

Communication skills

Team collaboration

Education

Bachelor's degree in Computer Science, Engineering or related field

Tools

Jenkins

Questa/VCS

Verdi

Job description

Synaptics is looking for a Senior Verification Engineer who will be part of SoC Verification team. Your primary focus will be working on IP and SoC Verification.

responsibilities :

• Develop System Verilog UVM testbenches and resolve complex test bench challenges
• Define and implement a functional coverage model to ensure complete design verification
• Develop a deep understanding of complex SoCs and IPs and take end-to-end ownership of their verification
• Contribute to verification strategy and architecture of SoC testbenches

requirements-expected :

• Strong proficiency in System Verilog and UVM
• Hands on experience using industry standard simulation & debugging tools i. e. Questa/VCS and Verdi etc.
• Good understanding of assertion-based verification methodologies and familiarity with Formal Verification tools
• Proficiency in scripting languages including Python, Perl, or Tcl
• Experience of automated systems (e. g. Jenkins), and versioning tools (GIT)
• C / C++ for embedded CPU verification an advantage
• Well organized with strong attention to detail; proactively ensures work is accurate
• Problem-solving skills through practical use of technology and a solid understanding of product architecture
• Excellent verbal and written communication skills, with the ability to articulate complex technical concepts clearly
• Strong team player with the ability to work collaboratively within a diverse cross-functional team
• Bachelor’s degree in Computer Science, Engineering or related field or equivalent
• 5+ years or equivalent of relevant experience in SoC verification

benefits :

• sharing the costs of sports activities
• private medical care
• sharing the costs of foreign language classes