Remote-Ready FPGA Engineer for HVDC MACH Systems

Hitachi Energy; Kraków; On-site; PLN 140,000 - 210,000; Full time

Benefits offered by this job

Private medical care

Life insurance

Fitness program access

Benefits platform with discounts

Employee Capital Plans (PPK)

Home office equipment / setup support

Spectacles/contact lenses allowance

Company events & team building

Psychological support program

Free parking

Job summary

Hitachi Energy Krakow is seeking an FPGA/ASIC design engineer with hands-on experience in VHDL/Verilog to join the MACH™ project within an R&D context. You will participate in the full development lifecycle of FPGA-based devices, develop and validate FPGA solutions, and collaborate with hardware, architecture, and software teams to ensure robust system integration.

You will translate requirements into implementable FPGA and system-level solutions, maintain documentation, and support prototype

Qualifications

• At least 2 years of experience in FPGA/ASIC design & simulation in VHDL (or Verilog).
• Good understanding of synchronous design, time constraining and static timing analysis.
• Experience in modelling in High Level Synthesis.
• Knowledge of GIT, CI/CD principles and Azure DevOps pipelines.
• Experience in self‑testing test‑benches and regression tests.
• Experience with laboratory equipment, prototyping and testing.
• Strong commitment to safe work practices and dedication to follow all relevant workplace safety guidelines.
• High level of self‑motivation, curiosity, and desire to learn about modern technologies.
• A collaborative, solutions‑oriented approach, and effective communication skills.

Responsibilities

• Participation in the full development lifecycle of FPGA-based devices, from requirements analysis and architecture definition through implementation, integration, validation, and deployment.
• Design, implementation, simulation, debugging, and maintenance of FPGA solutions using VHDL and modern AMD/Xilinx FPGA platforms.
• Investigation and evaluation of alternative technical approaches, supporting architectural decisions through feasibility studies, proof-of-concept development, and technical risk reduction activities.
• Development of reusable verification and validation infrastructure.
• Collaboration with hardware, architecture, and software teams to define interfaces, resolve cross-domain technical issues, and ensure successful system integration.
• Analysis and clarification of system requirements, translating high-level functional expectations into implementable FPGA and system-level solutions.
• Creation and maintenance of technical documentation, including interface specifications, design diagrams, test plans, and engineering guidelines.
• Support of prototype bring‑up, laboratory testing, and hardware validation activities on real target platforms.
• Contributing to knowledge sharing across engineering teams through technical reviews, design discussions, engineering presentations, and documentation of lessons learned.
• Participation in cross-functional planning, technical coordination, and engineering decision-making activities throughout the product development process.

Skills

VHDL

Verilog

FPGA design

ASIC design

Synchronous design

Timing analysis

High Level Synthesis

Git

CI/CD

Azure DevOps

Test-benches

Prototyping

Documentation

Team collaboration

Tools

Git

CI/CD

Azure DevOps

Job description

Hitachi Energy Krakow is seeking an FPGA/ASIC design engineer with hands-on experience in VHDL/Verilog to join the MACH™ project within an R&D context. You will participate in the full development lifecycle of FPGA-based devices, develop and validate FPGA solutions, and collaborate with hardware, architecture, and software teams to ensure robust system integration.

You will translate requirements into implementable FPGA and system-level solutions, maintain documentation, and support prototype