Hardware Verification Engineer

leading-edge; Islamabad; On-site; PKR 2,400,000 - 4,200,000; Full time

Job summary

leading-edge seeks a Hardware Verification Engineer with hands-on IP and SoC verification experience, including UVM environments, VIPs, and coverage-driven regression across digital IPs and subsystems.

The role involves leading verification of pipelines and peripherals such as UART, I3C, I2C, Ethernet, PCIe, and chiplet communications, while developing reusable verification environments and regression setups.

Qualifications

• Hands-on verification of IP and SoC-level designs.
• Experience building verification environments and testbenches.
• Proficiency with VIPs, simulators, and coverage-driven flows.

Responsibilities

• Lead verification of Match-Action Pipeline and UART/IPs with staged customer deliveries.
• Drive bring-up, test planning, and execution for UART, I3C, I2C, and Ethernet peripherals.
• Develop reusable APB protocol verification environments.
• Integrate commercial Ethernet VIPs at block and chip levels (800G/400G/100G).
• Create and execute UVM sequences for PCIe/CXL traffic generation and validation.
• Configure and verify I3C chiplet and HUB chiplet communications with processor cores.
• Validate NIC400 infrastructure and system address mapping for SoC flows.
• Perform CSR verification for Ethernet chiplets.
• Drive coverage closure (line, toggle, FSM) and establish regression setups.
• Automate Register Abstraction Layer (RAL) flows for efficient verification.

Skills

UVM methodology

SystemVerilog

VIPs and simulators

AMBA protocols (APB/AXI)

Ethernet, PCIe, I3C

Chiplet/IP integration

Tools

UVM testbenches

VIP integration frameworks

Coverage-driven verification

Job description

Job Title: Hardware Verification Engineer

Industry: Semiconductors / Embedded Systems / SoC Design

Job Summary:

We are seeking a skilled Hardware Verification Engineer with hands-on expertise in IP and SoC-level verification. The ideal candidate will have experience in developing verification environments, integrating VIPs, creating UVM testbenches, and executing coverage-driven regressions for various digital IPs and subsystems.

Key Responsibilities:

• Lead verification of Match-Action Pipeline and UART/IPs with staged customer deliveries.
• Drive bring-up, test planning, and execution for UART, I3C, I2C, and Ethernet peripherals.
• Develop reusable APB protocol verification environments.
• Integrate commercial Ethernet VIPs at block and chip levels (800G/400G/100G).
• Create and execute UVM sequences for PCIe/CXL traffic generation and validation.
• Configure and verify I3C chiplet and HUB chiplet communications with processor cores.
• Validate NIC400 infrastructure and system address mapping for SoC flows.
• Perform Control/Status Register (CSR) verification for Ethernet chiplets.
• Drive coverage closure (line, toggle, FSM) and establish regression setups.
• Automate Register Abstraction Layer (RAL) flows for efficient verification.

Preferred Skills:

• Strong command of UVM methodology and SystemVerilog.
• Experience with industry-standard VIPs and simulators.
• Deep understanding of AMBA protocols (APB, AXI), Ethernet, PCIe, I3C.
• Familiarity with chiplet-based architecture and IP integration.