Staff Engineer, IP Design

Lattice Semiconductor; Penang; On-site; MYR 120,000 - 160,000; Full time

Job summary

A leading technology company is seeking a Staff IP Design Engineer in Penang, Malaysia. The ideal candidate will have extensive experience in high-speed SERDES protocols and FPGA RTL design, with strong programming skills in C/C++, Perl, TCL, or Python. This role offers the opportunity to work in a dynamic, team-oriented environment focused on innovation. Join us to contribute to groundbreaking connectivity solutions!

Qualifications

• 10+ years of system design experience (8 for MS, 6 for PhD).
• Independent, self-motivated, and capable in dynamic environments.
• Innovative problem solver with good communication skills.

Responsibilities

• Build Connectivity IP portfolios for Lattice FPGA.
• Translate specifications into high-speed RTL design.
• Collaborate closely with architects on design projects.

Skills

High speed SERDES protocols

FPGA RTL design

Programming (C/C++, Perl, TCL, Python)

Logic verification

Debugging and timing closure

Education

BS/MS/PhD in Electronics or Computer Engineering

Job description

Lattice Overview

There is energy here8 energy you can feel crackling at any of our international locations. Its an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality. Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you9re looking for.

Responsibilities & Skills

We are seeking a Staff IP Design engineer, passionate individual with technical leadership capabilities to build Connectivity IP portfolios for Lattice FPGA. The individual should have the ability to work closely with architect to translate specifications into high-speed RTL design, for the best Performance, Power and logic utilization.

Requirements

Key Skills:

• Experience in high speed SERDES protocols (e.g.: PCIe, Ethernet, CPRI or JESD204B/C) or Peripherals (SPI, I2C or I3C) is a must.
• Hands-on experience in FPGA RTL design, logic verification, debug and timing closure are essential
• Programming skills (e.g.: C/C++, Perl, TCL or Python).
• Experience in hardware validation or hardware interoperability test is a plus.
• Experience in soft IP packaging, example design and testbench development will be an added advantage.

Education and General:

• BS/MS/PhD in Electronics or Computer Engineering minimum of 10 years (8 for MS and 6 for PhD) of system design experience.
• Independent and self-motivated, capable of executing under dynamic environment and uncertainties.
• Innovative, problem solver who likes to come up with newer and better solutions for existing problems.
• Individual who works well with a team of diverse engineers, open to feedback and opinions.
• Able to galvanize and enable a team to execute on a project to completion.
• Good communication skill.