Silicon Packaging Architect

Intel; George Town; On-site; MYR 100,000 - 150,000; Full time

Job summary

A leading technology company in Penang is seeking an experienced professional in package design. The role involves translating product requirements, leading technology decisions, and ensuring high-quality package output. Candidates must have a Bachelor's degree in a relevant engineering field and at least 10 years of experience. This position offers an opportunity to work on innovative solutions in a dynamic environment.

Qualifications

• Minimum 10 years of experience in package design and/or architecture.
• Prior leadership role in package technology readiness and design tape-out.

Responsibilities

• Translate product requirements into package architecture.
• Lead technology tradeoff decisions for silicon packages.
• Collaborate with teams to ensure quality package output.
• Oversee end-to-end package development process.
• Provide innovative and cost-effective packaging solutions.

Skills

Package design expertise

Problem-solving

Leadership

Collaboration

Education

Bachelor Degree in engineering/science

Job description

Job Details:

• Translates product requirements into package architecture specification, drives end-to-end package solutions for physical, electrical, and cost requirements.
• Leads technology tradeoff decisions ensuring silicon packages conform to electrical, mechanical, thermal, and reliability standards, specifications, and landing zones.
• Collaborates with silicon, hardware, and package leads to ensure high quality package output and aids in removing roadblocks.
• Oversees end-to-end package development process, including design, processes, and procedures and continuously improves packaging quality standards and targets.
• Applies expertise in package design troubleshooting, resolves new and existing packaging problems involving designs, materials, and processes and provides innovative and cost-effective solutions.
• Collaborates with manufacturing team to ensure the packaging design and tape-out seamlessly transition to production.

Qualifications:

• Bachelor Degree in relevant engineering/science domain with minimum 10 years of experience in the package design and/or architecture.
• Prior leadership role in package technology readiness development, design tape-out and/or innovation.

Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to our staffing team at [e-mail].

Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Malaysia, Penang Business group: Intel makes possible the most amazing experiences of the future. You may know us for our processors. But we do so much more. Intel invents at the boundaries of technology to make amazing experiences possible for business and society, and for every person on Earth. Harnessing the capability of the cloud, the ubiquity of the Internet of Things, the latest advances in memory and programmable solutions, and the promise of always-on 5G connectivity, Intel is disrupting industries and solving global challenges. Leading on policy, diversity, inclusion, education and sustainability, we create value for our stockholders, customers, and society. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust: N/A

Work Model for this Role

* Job posting details (such as work model, location or time type) are subject to change.