Senior Staff Design Verification Engineer

Advanced Micro Devices Global Services (M) Sdn. Bhd.; Penang; On-site; MYR 100,000 - 140,000; Full time

Job summary

A leading technology firm in Penang is seeking a Senior/Staff Hardware Digital Engineer to drive the verification of High Speed IO Protocol IPs. Candidates should have a strong background in IP ASIC verification, debugging, and experience with modern verification tools and methodologies. This role requires collaboration across various teams to ensure high-quality designs. Competitive benefits are provided.

Qualifications

• Strong analytical and problem-solving skills.
• Experience collaborating with engineers across different locations.
• Hands-on experience with verification methodologies and tools.

Responsibilities

• Lead projects and solve technical issues with suggested solutions.
• Collaborate with engineers to understand new features to verify.
• Build and estimate test plan documentation and verification tests.
• Debug test failures and work with engineers to resolve design defects.
• Review functional metrics to meet coverage requirements.

Skills

IP level ASIC verification

Debugging firmware and RTL code

UVM testbenches

Linux and Windows environments

Verilog

SystemVerilog

C

C++

USB protocols

UFS protocols

Ethernet protocols

PCIe protocols

Scripting languages like Perl

Power aware simulations

SystemC

TLM

Education

Bachelor’s or Master’s degree in Computer Engineering

Job description

Job Title

Senior/Staff Hardware Digital Engineer (Board Level Design)

Company

NI Malaysia Sdn Bhd

THE ROLE

As a member of the Central Engineering Group, you will help bring to life cutting‑edge designs. The focus of this role is to plan, build, and execute the verification of new and existing features for High Speed IO Protocol IPs (USB, PCIe, Ethernet, UFS) that are used in AMD’s product portfolio, resulting in no bugs in the final design.

THE PERSON

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player with excellent communication skills and experience collaborating with engineers located in different sites/timezones. You have strong analytical and problem‑solving skills and are willing to learn and ready to take on problems.

KEY RESPONSIBILITIES

• Able to lead project and resolve technical issues with solutions suggested.
• Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified.
• Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases.
• Estimate the time required to write the new feature tests and any required changes to the test environment.
• Build the directed and random verification tests.
• Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues.
• Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements.

PREFERRED EXPERIENCE

• Proficient in IP level ASIC verification.
• Proficient in debugging firmware and RTL code using simulation tools.
• Proficient in using UVM testbenches and working in Linux and Windows environments.
• Strong background with UVM, Verilog, SystemVerilog, C, and C++.
• Knowledge of USB, UFS, Ethernet, PCIe, AXI is a plus.
• Developing UVM based verification frameworks and testbenches, processes and flows.
• Automating workflows in a distributed compute environment.
• Exposure to power aware simulations is a plus.
• Good understanding and hands‑on experience in the UVM concepts and SystemVerilog language (SVA, UVM scoreboard).
• Good working knowledge of SystemC and TLM with some related experience.
• Scripting language experience: Perl, Ruby, Makefile, shell preferred.
• Exposure to leadership or mentorship is an asset.
• Over 11 years of digital IP verification with SV/UVM/formal verification or new methodology of the industry.

ACADEMIC CREDENTIALS

• Bachelor’s or Master’s degree in Computer Engineering or Electrical Engineering.

LOCATION

Penang, Malaysia