Senior Silicon Design Engineer

AMD; Malaysia; Hybrid; MYR 120,000 - 180,000; Full time

Benefits offered by this job

AMD benefits at a glance

Hybrid work arrangement

Job summary

AMD is seeking a Front-End silicon design engineer in Penang, Malaysia, to work within the AECG ASIC/Custom silicon team. You will translate chip specifications into RTL, integrate IPs, and drive front-end design across multi-clock domains with SystemVerilog, VHDL, and Verilog.

The role requires hands-on RTL coding, experience with clocking and power management, and a focus on bug-free, synthesizable code. A hybrid work setup in Penang is offered with collaboration across firmware and software

Qualifications

• Hands on RTL coding, including IP RTL integration.
• Strong SOC clocking, reset, boot and power management understanding.
• Experience with CDC, Lint, VCLP, LEC quality checks.

Responsibilities

• Convert chip spec to RTL using internal and external IPs.
• Plan and deliver IP level RTL, implement front-end RTL integration.
• Define and debug SDC timing constraints and SystemVerilog test benches.
• Create readable Verilog RTL and SV assertions for coverage improvement.
• Participate in post-silicon functional and performance debugging.

Skills

RTL Verilog

VHDL

SystemVerilog

Scripting (Python)

Scripting (Perl)

Shell scripting

Spyglass

Synthesis/LEC flow

SDC timing constraints

Independent work

Education

Bachelor's or Master's in Computer/Electrical Engineering

Tools

Spyglass

Synthesis tools

Job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believetechnology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMDis shapingthefuture.

Whetheryou’redesigning next-gen processors, enabling AI breakthroughs, orbringing leading edge products to market, every role at AMD contributes to something bigger— technologythat moves the world forward.Join us and, together, we’ll advance your career.

THE ROLE:

As part of the AECG ASIC/Custom silicon team, we are looking for an adaptive, self-motivative Front-End silicon design engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market.

THE PERSON:

As a Front-End silicon design engineer/SOC RTL Integration Engineer, you will work with chip architects to conceive design, help with architecture/product definition through early involvement in the product life-cycle.

KEY RESPONSIBILITIES:

• Convert chip spec to RTL using internal and external IPs
• Plan/deliver IP level RTL, and implement front-end RTL integration
• Experience in ASIC/SoC front-end (preferably RTL Verilog and VHDL based) design and methodologies.
• Knowledge in frontend design experience on IPs involve processor based sub-system, Serial Standard interfaces, Memory controllers
• Exposure to Low-power design, System Security considered as added advantage
• Hands on front-end design of complex multi clock domain blocks
• Fluency in design & verification languages such as VHDL, Verilog, and System Verilog.
• Good in scripting, ie. TCL, shell script, Perl, Python
• Experience in Spyglass for lint and CDC checks.
• Experience in synthesis and LEC flow.
• Experience in identifying and implementing complex ECO in netlist.
• Defining and debugging SDC timing constraints.
• Knowledge on Verification Methodologies to actively participate in Debug Analysis.
• Knowledge about system level flows and interaction with Firmware and Software would be added advantage.
• Optimize the design to meet power, performance, area and timing requirements
• Write easily readable and synthesizable Verilog RTL
• Run unit level testing to deliver quality code to the Design Verification Team
• Create assertions to improve coverage and cover points to analyze coverage of the design
• Create well written block level design documentation
• Participate in post silicon functional and performance debug and tuning
• Self-driven and capable for independent work and independent decision making.
• Mentor junior engineers

PREFERRED EXPERIENCE:

• Hands on experience in RTL coding required, including IP RTL integration
• Strong understanding of SOC like clocking, reset, boot and power management flows, low power design techniques, security
• Expertise with quality checks like CDC, Lint, VCLP, LEC
• Strong technical engineer who communicates well with great collaboration skills
• Experience in RISC-V, NOC, DMA, bus interfaces ie. APB, AHB, AXI, OBI
• Experience in IPs like PCIe & DDR4/5 will be an advantage
• Experience in packet processing, wireless protocols etc.
• Experience in wireless, base station protocols will be helpful (CPRI, JESD, Uplink/Downlink) would be

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in computer engineering/Electrical Engineering

LOCATION:

Penang, Malaysia

#LI-KL1

#LI-Hybrid

Benefits offered are described: AMD benefits at a glance.

AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.