TLM Developer

Purview Services; New Delhi; On-site; INR 1,200,000 - 2,100,000; Full time

Job summary

Purview Services in Delhi, India seeks an experienced hardware modeling engineer to develop and maintain TLM 2.0/SystemC models for SoC components, and to create transaction-level models for IP blocks, processors, memories, buses and interconnects.

You will implement TLM sockets and interfaces, develop functional and performance models for co-simulation, collaborate with RTL, firmware, verification, architecture and software teams, and optimize models for simulation speed and accuracy.

Qualifications

• 5-9 years of experience in TLM/SystemC development or hardware modeling.
• Strong hands-on experience with C++ and SystemC.
• Good knowledge of TLM 2.0 and transaction-level modeling concepts.
• Experience with TLM sockets, payloads, interfaces, and communication mechanisms.
• Understanding of SoC architecture, buses, memories, processors, and hardware interfaces.
• Knowledge of RTL concepts and Verilog/SystemVerilog is preferred.
• Experience with simulation/debugging tools and Linux environments.
• Knowledge of virtual prototyping or hardware/software co-simulation is an advantage.
• Strong debugging, analytical, and problem-solving skills.
• Good communication and collaboration abilities.

Responsibilities

• Develop and maintain TLM 2.0 / SystemC models for SoC and hardware components.
• Create transaction-level models for IP blocks, processors, memories, buses, peripherals, and interconnects.
• Implement and integrate TLM sockets, initiator/target interfaces, and communication channels.
• Develop functional and performance models for hardware/software co-simulation.
• Work with hardware and verification teams to understand specifications and modeling requirements.
• Develop reusable and configurable TLM components.
• Integrate TLM models with simulation and verification environments.
• Debug functional, timing, communication, and integration issues in SystemC/TLM models.
• Develop test scenarios and validate model behavior against RTL/specifications.
• Support virtual platforms and early software development using TLM models.
• Optimize models for simulation performance and accuracy.
• Perform code reviews and maintain coding standards and technical documentation.
• Collaborate with RTL, firmware, verification, architecture, and software teams.
• Support model integration, regression testing, and continuous verification activities.

Skills

TLM/SystemC

C++

SystemC

SoC architecture

RTL & Verilog

Linux environments

Job description

Key Responsibilities:

• Develop and maintain TLM 2.0 / SystemC models for SoC and hardware components.


• Create transaction-level models for IP blocks, processors, memories, buses, peripherals, and interconnects.


• Implement and integrate TLM sockets, initiator/target interfaces, and communication channels.


• Develop functional and performance models for hardware/software co-simulation.


• Work with hardware and verification teams to understand specifications and modeling requirements.


• Develop reusable and configurable TLM components.


• Integrate TLM models with simulation and verification environments.


• Debug functional, timing, communication, and integration issues in SystemC/TLM models.


• Develop test scenarios and validate model behavior against RTL/specifications.


• Support virtual platforms and early software development using TLM models.


• Optimize models for simulation performance and accuracy.


• Perform code reviews and maintain coding standards and technical documentation.


• Collaborate with RTL, firmware, verification, architecture, and software teams.


• Support model integration, regression testing, and continuous verification activities.

Required Skills & Qualifications:

• 5-9 years of experience in TLM/SystemC development or hardware modeling.


• Strong hands‑on experience with C++ and SystemC.


• Good knowledge of TLM 2.0 and transaction-level modeling concepts.


• Experience with TLM sockets, payloads, interfaces, and communication mechanisms.


• Understanding of SoC architecture, buses, memories, processors, and hardware interfaces.


• Knowledge of RTL concepts and Verilog/SystemVerilog is preferred.


• Experience with simulation/debugging tools and Linux environments.


• Knowledge of virtual prototyping or hardware/software co‑simulation is an advantage.


• Strong debugging, analytical, and problem‑solving skills.


• Good communication and collaboration abilities.