Technical Staff Engineer - Design

Microchip Technology; India; On-site; INR 5,000,000 - 7,000,000; Full time

Job summary

Microchip Technology invites a seasoned Staff Design Engineer to join the Data Center Solutions group. You will drive pad ring planning, IO cell placement, and bump pattern definitions for next-gen memory and storage controllers, collaborating across architecture, packaging, and manufacturing teams.

You will own IO connectivity deliverables, verify designs with Verilog netlists and pad ring DEFs, and contribute to silicon validation and debug efforts, leveraging Experiencing in Orbit IO and ISP

Qualifications

• Bachelor's degree in Electrical Engineering with 12+ years related experience.
• Hands-on experience with pad ring planning, IO cell placement, and bump map/pattern definition for advanced SoC designs.
• Knowledge of IO library cells, IO standards, and PHY-level IO interfaces (SerDes, DDR, PCIe, CXL).
• Experience with IO planning and implementation EDA tools (Orbit IO, ISP).
• Experience generating and validating IO connectivity deliverables (pad ring DEF, IO netlist, bump assignment).
• Understanding of Foundation and Hard IP views including RTL, lef and liberty.
• Scripting in Tcl and/or Python for flow automation.
• Excellent analytical and communication skills.

Responsibilities

• Own design planning and construction of pad rings, bump patterns for IO.
• Develop, implement, and maintain IO connectivity, pad ring definitions, and bump designs through the design cycle.
• Generate and validate physical design handoff deliverables (pad ring DEFs, Verilog netlists, bump maps).
• Ensure IO/pad ring designs meet design standards and constraints.
• Collaborate with Architecture, Product Design, Packaging, Implementation, and Foundry teams on IO/package requirements.
• Support verification, emulation, ASIC validation, and silicon debug by analyzing IO issues and driving improvements.

Skills

Pad ring planning

IO cell placement

Bump map/pattern definition

IO standards

SerDes/DDR/PCIe/CXL interfaces

EDA tools (Orbit IO, ISP)

IO connectivity hand-off

Flow automation (tcl/python)

Verilog netlists

Education

Bachelor's degree in Electrical Engineering

MS degree in Electrical Engineering

Tools

Orbit IO

ISP (EDA)

Job description

Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.

People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip's nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values ; we affectionately refer to it as the Aggregate System and it's won us countless awards for diversity and workplace excellence.

Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.

Job Description:

The successful candidate will join the rapidly growing Data Center Solutions (DCS) business unit at Microchip. DCS has a broad portfolio of products widely deployed by the industry's cutting-edge server/storage OEMs and hyperscale datacenters. Customers deploy DCS solutions into applications ranging from Big Data capacity storage to artificial intelligence and machine learning that are helping to shape the next digital age. Our product portfolio includes SAS/PCIe/NVMe/CXL products that connect, manage, and secure the world's information, including Flash Controllers, High Performance Switches, RAID Controllers and Memory Controllers. Join a team where you can expand your skill set and drive key elements of the industry's technology leadership.

An opening exists for Tech Staff Design Engineer with an interest in developing the next generation of storage and memory controller SoC products. This will involve taking a design from initial concept through to production. Throughout you will work beside experienced engineers and be exposed to Microchip's Best-In-Class engineering practices. Working side-by-side with some of the brightest minds and most innovative people in the industry, you won't just fill a position, you will be given an opportunity to work on a team where your contributions matter. Microchip fosters continuous learning in a challenging and rewarding environment.

As a Staff Design Engineer, your job will entail the following:

• Own design planning and construction of pad rings, bump patterns, ensuring alignment with package and system-level constraints.
• Develop, implement, and maintain IO connectivity, pad ring definitions, and bump pattern designs throughout the design cycle.
• Generate and validate physical design handoff deliverables including pad ring DEF files, Verilog netlists, bump maps, and associated implementation data for downstream teams.
• Ensure IO and pad ring designs comply with design standards, package constraints, and implementation best practices.
• Collaborate with Architecture, Product Design, Internal IP Packaging, Implementation, Product Engineering, Technology Development, and Foundry teams to align on IO/package requirements and resolve technical issues.
• Support Verification, Emulation, ASIC validation, and silicon debug efforts by analyzing IO-related issues and driving design improvements.

Requirements/Qualifications:

• B.S degree in electrical engineering with 12+ years related experience.
• Hands-on experience with pad ring planning, IO cell placement, and bump map/pattern definition for advanced SoC designs.
• Knowledge of IO library cells, IO standards, and PHY-level IO interfaces (SerDes, DDR, PCIe, CXL).
• Experience with IO planning and implementation EDA tools (e.g., Orbit IO, ISP or equivalent); specific tool experience is valuable but not mandatory.
• Experience generating and validating IO connectivity deliverables (pad ring DEF, IO netlist, bump assignment) for physical design hand-off).
• Understanding of Foundation and Hard IP related views including RTL, lef and liberty
• Working proficiency in flow automation and scripting using tcl and/or python
• Excellent analytical, communication (written and verbal), and documentation skills.

Preferred qualifications:

• M.S degree in electrical engineering
• Basic understanding of DFT methodologies mainly JTAG/Boundary Scan (IEEE 1149.1) architecture and TAP controller operation for inc